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A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation 具有宽供电范围的体偏置发生器，低至阈值电压，用于模内可变性补偿
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008858
Norihiro Kamae, Islam A. K. M. Mahfuzul, A. Tsuchiya, H. Onodera
{"title":"A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation","authors":"Norihiro Kamae, Islam A. K. M. Mahfuzul, A. Tsuchiya, H. Onodera","doi":"10.1109/ASSCC.2014.7008858","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008858","url":null,"abstract":"A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. While FGBB is effective in reducing variability and power consumption, a number of BBGs are required on a die and therefore simplified design of BBGs is necessary. This paper proposes a cell-based design of a BBG that generates forward and reverse body bias voltages only from a core supply voltage ranging from the near threshold of 500mV to the nominal voltage of 1.2V. This wide operating range is achieved by a low voltage error amplifier with a Vth biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm low power CMOS process to control 0.22mm2 of core circuit with the area overhead of 2.3% for the BBG.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122732314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Mobile display technologies: Past, present and future 移动显示技术:过去、现在和未来
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008845
H. Ohshima
{"title":"Mobile display technologies: Past, present and future","authors":"H. Ohshima","doi":"10.1109/ASSCC.2014.7008845","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008845","url":null,"abstract":"Over the years, full-color flat panel displays, represented by thin-film-transistor (TFT) liquid crystal displays (LCD), have enabled many new applications, such as the digital camera, notebook PC and thin, flat-screen TV, through intensive research activities around the world. Recently, small-sized mobile display development has been leading the R&D effort to support the severe requirements of smartphones and tablet PCs. For the displays used in those applications, high definition, high visual quality, low power consumption, small form factor and easy-to-use touch userinterface (UI) are critical values. Trends exhibit that even higher pixel density and lower power consumption will be required for future smart devices. In this presentation, the mobile display market and recent technical achievements are reviewed. In addition, expectations for semiconductor technologies to enable the development of future displays and user interfaces will be discussed.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122026753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS 一种基于28nm CMOS的带数字ELD补偿的0.022mm2 98.5dB SNDR混合音频δ - σ调制器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008924
Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu
{"title":"A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS","authors":"Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu","doi":"10.1109/ASSCC.2014.7008924","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008924","url":null,"abstract":"An area-efficient hybrid ΔΣ modulator with a 6-bit shared asynchronous successive approximation register (ASAR) quantizer for audio application is proposed and demonstrated in a 28nm CMOS process. The modulator incorporates a 1st-order analog filter and a 1st-order digital filter, which enables high integration of digital signal processing at low power and small area. The 1st-order digital filter is developed to replace the second analog integrator and results in significant area reduction. Moreover, the proposed digital filter provides digital excess loop delay (ELD) compensation and eliminates the conventional analog ELD feedback DAC. In addition, R-DAC is adopted to alleviate the flicker noise issue in 28nm process. The measured result shows 98.5dB SNDR and 100.6dB DR within 24kHz bandwidth, while occupying 0.022mm2 and achieving a FoM of 343fJ/conv. (Power/(2BW·2ENOB)) or 173.8dB (DR+10*log(BW/Power)).","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123519800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop 一个2×25 Gb/s时钟和数据恢复与背景锁幅环路
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008915
Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu
{"title":"A 2×25 Gb/s clock and data recovery with background amplitude-locked loop","authors":"Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2014.7008915","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008915","url":null,"abstract":"A 2×25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 27-1. It dissipates 8.8 mw per channel from 1.15 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132373713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability 具有10年数据保留能力的2.4 pJ铁电非易失性触发器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008850
H. Kimura, T. Fuchikami, K. Marumoto, Y. Fujimori, S. Izumi, H. Kawaguchi, M. Yoshimoto
{"title":"A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability","authors":"H. Kimura, T. Fuchikami, K. Marumoto, Y. Fujimori, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ASSCC.2014.7008850","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008850","url":null,"abstract":"A ferroelectric-based (FE-based) non-volatile flip-flop (NWF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size while maintaining a wide read voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year, 85°C data retention capability. An access speed of FE capacitors can be adaptively changed according to required retention time, which becomes 1.6/fS for 10-year data retention, and 170ns for 10-hour data retention. Especially, short-term data retention is suitable for power gating implementation. Applying the proposed circuitry in 32bit CPU of a vital sensor LSI, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr, Ti)O3(PZT) thin films.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132029049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection 基于δ调制的尖峰检测的0.5 v亚μ w /通道神经记录IC
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008892
Seong-Jin Kim, Lei Liu, Lei Yao, W. Goh, Yuan Gao, M. Je
{"title":"A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection","authors":"Seong-Jin Kim, Lei Liu, Lei Yao, W. Goh, Yuan Gao, M. Je","doi":"10.1109/ASSCC.2014.7008892","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008892","url":null,"abstract":"A neural recording IC with a new spike detection scheme is proposed to minimize power dissipation while preserving the waveform information of the detected spikes. A delta modulator is employed in the recording IC to reduce signal dynamic range and enable low-voltage operation. A series of output values from the delta modulator are stored in a small amount of analog memory to extract two key features of the neural signal - amplitude and frequency, which are used for accurate spike detection. Using the stored delta values, the precise spike waveform information can be conserved. A prototype recording IC with 16 channels has been fabricated using 0.18-μm CMOS technology. Measurement results demonstrate the spike detection capability successfully. The fabricated IC consumes only 0.88 μW/channel at 0.5-V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132094417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance check 具有闭环功率控制、有源电荷平衡和电极阻抗检测功能的符合20v的植入式神经刺激器集成电路
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008895
Lei Yao, Jianming Zhao, Peng Li, Rui-Feng Xue, Y. Xu, M. Je
{"title":"A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance check","authors":"Lei Yao, Jianming Zhao, Peng Li, Rui-Feng Xue, Y. Xu, M. Je","doi":"10.1109/ASSCC.2014.7008895","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008895","url":null,"abstract":"An inductively powered implantable neural stimulator IC is presented in this paper. It features closed-loop power control, active charge balancing, and electrode impedance check functions. The stimulator IC is powered through 13.56MHz inductive link and supports 33.3kbps bi-directional telemetry with ASK for forward command transmission and LSK for backward data transmission, achieving 20V high compliance voltage, maximum 1.24mA stimulation current, and the resting potential of 50mV. The IC has an active area of 2mm×2mm implemented in 0.18-μm CMOS process with 24V LDMOS option.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125492539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 16.6μW 32.8MHz monolithic CMOS relaxation oscillator 16.6μW 32.8MHz单片CMOS弛豫振荡器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008885
Yat-Hei Lam, Seong-Jin Kim
{"title":"A 16.6μW 32.8MHz monolithic CMOS relaxation oscillator","authors":"Yat-Hei Lam, Seong-Jin Kim","doi":"10.1109/ASSCC.2014.7008885","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008885","url":null,"abstract":"This paper presents a 32.8MHz low power, supply insensitive monolithic CMOS relaxation oscillator. Instead of using voltage-mode comparators for cycle-to-cycle capacitor voltage swing (CVS) threshold voltage comparison, the CVS is regulated by a low-power closed-loop control which consists of a current-controlled delay cell (CCDC), a Gm-C error integrator and a comparator-free switch logic block. The CCDC and switching logics are powered by a logic supply regulator for reducing switching-losses and line sensitivity. The oscillator consumes 16.6μW from a 1.5V supply voltage at room temperature, achieving a FOM of 0.51μW/MHz. The measured output frequency variation is <;±0.13%/V @ 32.8MHz, for a supply range of 1.5V to 3.6V It occupies 0.013mm2 in a 0.18μm CMOS process.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low-power single-chip transceiver for 169/300/400/900 MHz band wireless sensor networks 低功耗单片收发器，用于169/300/400/900 MHz频段无线传感器网络
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008848
M. Oba, Eiji Okada, A. Tachibana, Koji Takahashi, Masahiko Sagisaka
{"title":"A low-power single-chip transceiver for 169/300/400/900 MHz band wireless sensor networks","authors":"M. Oba, Eiji Okada, A. Tachibana, Koji Takahashi, Masahiko Sagisaka","doi":"10.1109/ASSCC.2014.7008848","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008848","url":null,"abstract":"A low-power transceiver for wireless sensor networks at sub-GHz frequency bands is presented, which integrates an RF frontend as well as a digital baseband and a MAC layer into a single 3.0 mm2 chip. The transceiver covers 169/300/400/900 MHz bands and supports FSK/GFSK modulation with a data rate from 1.2 to 200 kbps. A prototype is fabricated in 65 nm CMOS, achieving only 8.2 mA in the RX and 23 mA in the TX with +10 dBm output power at 915 MHz from a 3.3 V supply.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126369431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network 体域网用1-100Mb /s的0.5-9.9mW LDPC卷积码解码器
2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI: 10.1109/ASSCC.2014.7008902
Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee
{"title":"A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network","authors":"Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ASSCC.2014.7008902","DOIUrl":"https://doi.org/10.1109/ASSCC.2014.7008902","url":null,"abstract":"A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1~100Mb/s with power consumption of 0.5~9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.","PeriodicalId":161031,"journal":{"name":"2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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