体域网用1-100Mb /s的0.5-9.9mW LDPC卷积码解码器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008902

Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee

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引用次数: 4

摘要

采用90nm CMOS技术实现了低功耗LDPC卷积码解码器。提出了一种新的基于移位/共享内存架构的FEC候选方案，用于IEEE 802.15.4g和802.15.6体域网络应用。测量结果表明:(1)在0.6V供电电压下，解码器功耗为0.5~9.9mW，达到1~100Mb/s;(2)在相同硅面积下，与Viterbi解码器相比，具有更好的纠错性能。

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A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1~100Mb/s with power consumption of 0.5~9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.

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来源期刊

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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