A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network

Abstract

A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the decoder achieves (1) 1~100Mb/s with power consumption of 0.5~9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.