一种基于28nm CMOS的带数字ELD补偿的0.022mm2 98.5dB SNDR混合音频δ - σ调制器

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2014-11-01 DOI:10.1109/ASSCC.2014.7008924

Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu

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引用次数: 10

摘要

提出了一种用于音频应用的具有6位共享异步连续逼近寄存器(ASAR)量化器的面积高效混合ΔΣ调制器，并在28nm CMOS工艺中进行了演示。该调制器包含一个一阶模拟滤波器和一个一阶数字滤波器，可在低功耗和小面积下实现数字信号处理的高集成度。开发了一阶数字滤波器来取代二阶模拟积分器，并显著减小了面积。此外，所提出的数字滤波器提供数字过量环路延迟(ELD)补偿，并消除了传统的模拟ELD反馈DAC。此外，采用R-DAC来缓解28nm工艺中的闪烁噪声问题。测量结果显示，在24kHz带宽范围内，SNDR为98.5dB, DR为100.6dB，占用0.022mm2, FoM为343fJ/conv。(功率/(2BW·2ENOB))或173.8dB (DR+10*log(BW/功率))。

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A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS

An area-efficient hybrid ΔΣ modulator with a 6-bit shared asynchronous successive approximation register (ASAR) quantizer for audio application is proposed and demonstrated in a 28nm CMOS process. The modulator incorporates a 1st-order analog filter and a 1st-order digital filter, which enables high integration of digital signal processing at low power and small area. The 1st-order digital filter is developed to replace the second analog integrator and results in significant area reduction. Moreover, the proposed digital filter provides digital excess loop delay (ELD) compensation and eliminates the conventional analog ELD feedback DAC. In addition, R-DAC is adopted to alleviate the flicker noise issue in 28nm process. The measured result shows 98.5dB SNDR and 100.6dB DR within 24kHz bandwidth, while occupying 0.022mm2 and achieving a FoM of 343fJ/conv. (Power/(2BW·2ENOB)) or 173.8dB (DR+10*log(BW/Power)).

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2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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