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International Electron Devices Meeting 1991 [Technical Digest]最新文献

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Emission life expectancy of Ir-coated dispenser cathodes for CRTs 阴极射线管用涂有铱的分配器阴极的发射寿命
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235371
T. Higuchi, S. Matsumoto, T. Yakabe, Y. Sato, S. Koshigoe, T. Yoshii
{"title":"Emission life expectancy of Ir-coated dispenser cathodes for CRTs","authors":"T. Higuchi, S. Matsumoto, T. Yakabe, Y. Sato, S. Koshigoe, T. Yoshii","doi":"10.1109/IEDM.1991.235371","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235371","url":null,"abstract":"A compact Ir-coated dispenser cathode was developed for CRT (cathode ray tube) use. To study the emission life of the cathode, an accelerated life test was conducted, using 111% heater voltage. Oxide cathodes were also tested for comparison. The test indicated that the emission of the oxide cathodes decreased to 50% of normal after about 5000 hours. In comparison, after approximately 10000 hours, the emission of Ir-coated dispenser cathodes had decreased less than 5%. The 10000-hour-plus life expectancy of the Ir-coated dispenser cathode was modeled, with the results projecting a life expectancy of approximately 24000 hours at 111% heater voltage. It was estimated that, under normal conditions, the life expectancy of this Ir-coated dispenser cathode would be approximately 100000 hours.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"54 1","pages":"395-398"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88509996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-temperature superconducting resonator-stabilized coplanar hybrid-integrated oscillator at 6.5 GHz 6.5 GHz高温超导谐振腔稳定共面混合集成振荡器
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235275
R. Klieber, R. Ramisch, Robert Weigel, M. Schwab, R. Dill, A. Valenzuela, Peter Russer
{"title":"High-temperature superconducting resonator-stabilized coplanar hybrid-integrated oscillator at 6.5 GHz","authors":"R. Klieber, R. Ramisch, Robert Weigel, M. Schwab, R. Dill, A. Valenzuela, Peter Russer","doi":"10.1109/IEDM.1991.235275","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235275","url":null,"abstract":"A small-size coplanar oscillator has been designed and entirely fabricated on a 10-mm*10-mm/sup 2/ LaAlO/sub 3/ substrate in superconducting microwave integrated circuit (SMIC) technology. As an active element, a GaAs MESFET has been used. The oscillator is stabilized by a coplanar waveguide transmission line resonator patterned from a YBa/sub 2/Cu/sub 3/O/sub 7-x/ film onto the LaAlO/sub 3/ substrate. The oscillator, operating at 77 K, is characterized by a center frequency of 6.5 GHz and a power output of nearly 5 dBm. A single-sideband phase noise to carrier ratio of -90 dBc/Hz at 10-kHz offset has been attained. The attenuation of harmonics is better than 10 dBc.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"11 1","pages":"923-926"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86475851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology spotec是一种低于10 μ m/sup /双极晶体管结构，采用完全自对准侧壁多晶硅基技术
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235357
T. Shiba, Y. Tamaki, T. Onai, M. Saitoh, T. Kure, F. Murai, T. Nakamura
{"title":"SPOTEC-a sub-10- mu m/sup 2/ bipolar transistor structure using fully self-aligned sidewall polycide base technology","authors":"T. Shiba, Y. Tamaki, T. Onai, M. Saitoh, T. Kure, F. Murai, T. Nakamura","doi":"10.1109/IEDM.1991.235357","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235357","url":null,"abstract":"A novel structure for high-speed Si bipolar transistors has been developed and a 9.4- mu m/sup 2/ transistor is demonstrated. Transistors are fabricated with a new sidewall polycide base electrode technology (SPOTEC), narrow W plug metallization, narrow U-groove isolation, and 0.3- mu m lithography using an e-beam direct writing technique. SPOTEC is used to reduce the base electrode area. That is, CVD (chemical vapor deposited) W is selectively deposited on a sidewall surface of the polysilicon and is silicided. This technology makes a narrow and low-resistance base electrode (0.4 mu m wide and 10 Omega / Square Operator ) possible. The collector electrode is directly contacted on an n/sup +/ buried layer to reduce its area. The contact hole is filled with a low-resistance W plug by using selective W CVD technology. To reduce the isolation area, a narrow, deep U-groove is etched and refilled with CVD SiO/sub 2/. These four key techniques reduce the transistor area to less than 10 mu m/sup 2/. The shallow E-B junctions are formed using low-energy ion implantation and RTA (rapid thermal annealing). A high cutoff frequency of 38 GHz and small junction capacitances are obtained.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"59 3 1","pages":"455-458"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87725205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Physical basis and characteristics of light emission from quantized planar Ge structures 量子化平面锗结构光发射的物理基础和特性
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235363
R. Venkatasubramanian, D. Malta, M. Timmons, J. Hutchby
{"title":"Physical basis and characteristics of light emission from quantized planar Ge structures","authors":"R. Venkatasubramanian, D. Malta, M. Timmons, J. Hutchby","doi":"10.1109/IEDM.1991.235363","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235363","url":null,"abstract":"The characteristics of luminescence from quantized planar Ge structures are presented, showing stability with time, dependence on laser power excitation and temperature, and the presence of GaAs-Al/sub 0.8/Ga/sub 0.2/As overlayers. A single broad emission at 1.7 eV near 300 K is observed to become four distinct emissions at 2.16 eV, 2.01 eV, 1.696 eV, and 1.56 eV at 77 K. A model describing the basis of luminescence in small Ge structures is also presented. The increased probability for radiative recombination in the quantized structures is a result of states in the conduction band and valence band being closed in k-space than in bulk Ge. Thus, the luminescence at 1.7 eV in the quantized structures probably results from a one or two phonon-assisted process compared to a 4-5 phonon process in bulk Ge for photoluminescence at 0.7 eV.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"2017 1","pages":"429-432"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90373649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Gate-capacitance characteristics of deep-submicron LATID (large-angle-tilt implanted drain) MOSFETs 深亚微米大倾角植入漏极mosfet的栅极电容特性
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235375
T. Hori, Y. Odake, J. Hirase, T. Yasui
{"title":"Gate-capacitance characteristics of deep-submicron LATID (large-angle-tilt implanted drain) MOSFETs","authors":"T. Hori, Y. Odake, J. Hirase, T. Yasui","doi":"10.1109/IEDM.1991.235375","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235375","url":null,"abstract":"Gate-capacitance characteristics for LATID (large-angle-tilt implanted drain) devices are studied using high-resolution measurements and device simulation. As compared with single-S/D (source/drain), a deep-submicron LATID FET, developed to introduce sidewall spacers for reducing overlap length to approximately 0.09 mu m, is found to suppress gate-to-drain capacitance C/sub GD/ at 3.3 V operation by approximately 40%, to almost the same level as LDDs (lightly doped drains), while a LATID without spacers suffers from a >25% larger C/sub GD/. To suppress C/sub GD/, offsetting the n/sup +/ region by spacers is crucial, while the n/sup -/ region should remain fully overlapped with the gate to improve current drivability. Following this design guideline, the circuit speed of LATID can be improved by approximately 15% compared to LDDs. The deep-submicron LATID technology, with spacers, is promising for high-speed ULSI circuits.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"8 1","pages":"375-378"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90390355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Combining model development with characterization 将模型开发与特性描述相结合
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235260
D. Scharfetter, S. Duvall
{"title":"Combining model development with characterization","authors":"D. Scharfetter, S. Duvall","doi":"10.1109/IEDM.1991.235260","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235260","url":null,"abstract":"The authors demonstrate the advantages of combining model characterization with model development and implementation. Examples cover process and device simulators, compact models for circuit simulators, and statistical models for design verification of IC devices. Situations in which combining model characterization with design could have avoided miscorrelations identified during design verification are discussed.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"153 1","pages":"976-977"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73754406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new analytical model for low voltage hot electron taking Auger recombination as well as phonon scattering process into account 考虑俄歇复合和声子散射过程的低压热电子分析新模型
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235485
R. Shirota, T. Yamaguchi
{"title":"A new analytical model for low voltage hot electron taking Auger recombination as well as phonon scattering process into account","authors":"R. Shirota, T. Yamaguchi","doi":"10.1109/IEDM.1991.235485","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235485","url":null,"abstract":"The authors describe a novel accurate model and a numerical analysis of hot electron injection into the gate oxide of submicron MOSFETs in the low applied voltage region (V/sub GS/<5 V, V/sub DS/<3 V). The model quantitatively takes into account both the Auger recombination process and the phonon assist process. Calculated results agree with experimental results in the measured range of 2.3 V<V/sub DS/<2.7 V and 2.5 V<V/sub GS/<4.1 V. This agreement strongly indicates that the new model can give an accurate understanding of the injection mechanism, and successfully explains the low voltage hot electron phenomena.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"108 1","pages":"123-126"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74648538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ensemble Monte Carlo study of a novel heterojunction real-space transfer logic transistor (RSTLT) 新型异质结实空间转移逻辑晶体管(RSTLT)的集成蒙特卡罗研究
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235343
H. Tian, K.W. Kim, M. Littlejohn
{"title":"Ensemble Monte Carlo study of a novel heterojunction real-space transfer logic transistor (RSTLT)","authors":"H. Tian, K.W. Kim, M. Littlejohn","doi":"10.1109/IEDM.1991.235343","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235343","url":null,"abstract":"A novel real-space transfer logic transistor (RSTLT) is proposed based on the real-space transfer of hot electrons in a four-terminal heterojunction microstructure. Self-consistent steady-state and transient Monte Carlo simulations demonstrate that the RSTLT features both logic flexibility and ultra-fast switching speed. Calculated results show that the proposed RSTLT realizes NOT and EQUIVALENT logic functions in a single heterojunction device, and a conservative estimate of the characteristic switching time is approximately 3 psec.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"57 1","pages":"515-518"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74816866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High performance sub-half micron CMOS using rapid thermal processing 采用快速热处理的高性能亚半微米CMOS
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235414
R. Chapman, J. Kuehne, P. Ying, W. Richardson, A.R. Paterson, A. P. Lane, I. Chen, L. Velo, C. Blanton, M.M. Mosiehl, J. Paterson
{"title":"High performance sub-half micron CMOS using rapid thermal processing","authors":"R. Chapman, J. Kuehne, P. Ying, W. Richardson, A.R. Paterson, A. P. Lane, I. Chen, L. Velo, C. Blanton, M.M. Mosiehl, J. Paterson","doi":"10.1109/IEDM.1991.235414","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235414","url":null,"abstract":"A sub-half micron CMOS technology has been developed using rapid thermal processing (RTP) and a simplified process design. The threshold voltages are set high to permit operation above room temperature without excessive leakage. Novel process features include zero-topography well design, RTP CMOS well anneal in an ammonia ambient, RTP gate oxide, RTP source/drain anneal, and BPSG reflow at 750 degrees C in a high-pressure nitrogen ambient. Transistors with 8 nm gate oxide and 0.4 mu m gate lengths provide 65 ps gate delay at 3.3 V. The use of 4*10/sup 17//cm/sup 3/ CMOS well doping without added channel implants results in higher diode capacitance and increases inverter chain delay by approximately 20 ps/stage, but speeds less than 50 ps/stage should be obtained with L=0.3 mu m NMOS and L=0.4 mu m PMOS, both having effective channel lengths of approximately 0.2 mu m.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"43 1","pages":"101-104"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74258435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High-power, high-energy, and high-efficiency, phase-locked magnetron studies 大功率、高能、高效率锁相磁控管的研究
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235399
T. Treado, P. D. Brown, R. Bolton, T. Hansen, K. Eppley
{"title":"High-power, high-energy, and high-efficiency, phase-locked magnetron studies","authors":"T. Treado, P. D. Brown, R. Bolton, T. Hansen, K. Eppley","doi":"10.1109/IEDM.1991.235399","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235399","url":null,"abstract":"A 60-MW, 60% efficient, 35 J/pulse secondary emission magnetron at S-band has been developed. The authors report on experimental results from this moderate voltage (120-kV), repetitively pulsed (10-Hz), injection locked (14-15-dB-gain) magnetron. Results from particle-in-cell code computer simulations are presented which compare very well with the experiment when space-charge-limited emissions is assumed. By increasing the voltage, the drive power, and the magnetron length and by using a tungsten alloy anode, 120 MW should be achievable for approximately 4- mu s pulses at 130 kV with the pulse length limited by transient heating of the anode.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"48 1","pages":"597-600"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76565661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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