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International Electron Devices Meeting 1991 [Technical Digest]最新文献

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A self-aligned pocket implantation (SPI) technology for 0,. mu m-dual gate CMOS 一种自对准口袋植入(SPI)技术。双栅CMOS
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235390
A. Hori, S. Kameyama, M. Segawa, H. Shimomura, H. Ogawa
{"title":"A self-aligned pocket implantation (SPI) technology for 0,. mu m-dual gate CMOS","authors":"A. Hori, S. Kameyama, M. Segawa, H. Shimomura, H. Ogawa","doi":"10.1109/IEDM.1991.235390","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235390","url":null,"abstract":"A novel self-aligned pocket implantation (SPI) technology has been developed. This technology features a localized 'pocket' implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length Lg (the physical gate length) is 0.21 mu m. This process provides high punchthrough resistance and high current driving capability while maintaining low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 30% for N-MOSFET, and by 49% for P-MOSFET, compared to conventional LDD (lightly doped drain) devices. It is found that a dual gate CMOS fabricated by the SPI technology achieves high-speed circuit performance.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"8 1","pages":"641-644"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85443352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Mobility enhancement and quantum mechanical modeling in Ge/sub x/Si/sub 1-x/ channel MOSFETs from 90 to 300 K 90至300 K范围内Ge/sub -x/ Si/sub - 1-x/沟道mosfet的迁移率增强和量子力学建模
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235431
P. Garone, V. Venkataraman, J. Sturn
{"title":"Mobility enhancement and quantum mechanical modeling in Ge/sub x/Si/sub 1-x/ channel MOSFETs from 90 to 300 K","authors":"P. Garone, V. Venkataraman, J. Sturn","doi":"10.1109/IEDM.1991.235431","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235431","url":null,"abstract":"A peak hole inversion layer mobility of 290 cm/sup 2//V-s has been achieved at room temperature in Ge/sub x/Si/sub 1-x/ buried channel pMOSFETs. The peak mobility rises to 970 cm/sup 2//V-s at 90 K. This corresponds to a 50% enhancement in the effective mobility over Si control devices at room temperature and enhancements of over 100% at 90 K. The mobility of MOS-gated Ge/sub x/Si/sub 1-x/ buried channel transistors can be effectively modeled at room temperature by considering the dependence of the surface scattering on the average separation of carriers from the Si/SiO/sub 2/ interface. The mobility for devices with a 75-AA and a 105-AA Si spacer layer was tested and accurately modeled at room temperature using parameters extracted from a Si control device. At low temperatures ( approximately 90 K) an additional scattering term must be included to better fit the data. It is suggested that this additional term could result from alloy scattering in the Ge/sub x/Si/sub 1-x/ channel.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"6 Suppl 2 1","pages":"29-32"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81995436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Large-electromigration-resistance copper interconnect technology for sub-half-micron ULSI's 用于亚半微米ULSI的大电迁移电阻铜互连技术
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235447
T. Ohmi, T. Hoshi, T. Yoshie, T. Takewaki, M. Otsuki, T. Shibata, T. Nitta
{"title":"Large-electromigration-resistance copper interconnect technology for sub-half-micron ULSI's","authors":"T. Ohmi, T. Hoshi, T. Yoshie, T. Takewaki, M. Otsuki, T. Shibata, T. Nitta","doi":"10.1109/IEDM.1991.235447","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235447","url":null,"abstract":"A large-electromigration-resistance copper interconnect technology has been developed using the low-kinetic energy particle process. It was found that grains as large as 100 mu m grow in the copper film formed on SiO/sub 2/ upon the thermal annealing performed after the film growth process. The resistivity of the copper film is as low as 1.78 mu Omega cm at room temperature, which is almost identical to the bulk resistivity. The electromigration lifetime of the copper interconnect is three to five orders of magnitude larger than that of Al-Si-based alloy interconnects. Furthermore, a novel accelerated-electromigration-testing method has been developed to evaluate such long-lifetime copper interconnects within a short period of test time. The method has made it possible to perform comparative studies of various interconnect materials in a very efficient way to establish large-electromigration-resistance interconnection technology.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"11 1","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82018747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Hot-carrier effects in surface-channel PMOSFETs with BF/sub 2/- or boron-implanted gates 带有BF/sub /-或硼注入栅极的表面沟道pmosfet中的热载子效应
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235339
T. Mogami, L.E.G. Johansson, I. Sakai, M. Fukuma
{"title":"Hot-carrier effects in surface-channel PMOSFETs with BF/sub 2/- or boron-implanted gates","authors":"T. Mogami, L.E.G. Johansson, I. Sakai, M. Fukuma","doi":"10.1109/IEDM.1991.235339","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235339","url":null,"abstract":"Hot-carrier effects for surface-channel PMOSFETs with p/sup +/ poly-Si gates were investigated. When the annealing temperature is higher and the gate oxide thickness is thinner, larger boron penetration is observed for p/sup +/ poly-Si PMOSFETs. As a dopant for poly-Si gates, BF/sub 2/ causes larger boron penetration. However, PMOSFET lifetime does not depend on the degree of boron penetration, but on doping species (BF/sub 2/ or boron). PMOSFETs with BF/sub 2/-implanted gates have about 100 times longer lifetime than those with boron-implanted gates, because electron trapping in the gate oxide with the BF/sub 2/-implanted gate is smaller due to the incorporation of fluorine. The maximum allowed supply voltage, based on the hot-carrier reliability, is higher than mod -4 mod V for sub half-micron PMOSFETs with p/sup +/ poly Si gates.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"10 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82413233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Characterization of gyrating electron beams with a pinhole analyzer 用针孔分析仪表征旋转电子束
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235368
J. McAdoo, A. Kinkead, M. Sucy, A. Singh, M. Naiman
{"title":"Characterization of gyrating electron beams with a pinhole analyzer","authors":"J. McAdoo, A. Kinkead, M. Sucy, A. Singh, M. Naiman","doi":"10.1109/IEDM.1991.235368","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235368","url":null,"abstract":"An instrument for characterizing gyrating electron beams has been built and tested on an annular gyrating beam. Measurements of Larmor radius, axial period, guiding center locations, axial velocity spread, azimuthal velocity spread, and energy spread, all as functions of radial position within a beam, are reported. The instrument consists of a stationary pinhole foil, a rotable slit foil, and a translatable phosphor screen for detecting electrons that pass through the slit and pinhole. The beam used for prototype tests had a current of 0.6 A, an energy of 16.5 kV, a Larmor radius of 3 mm, and an axial period of 35 mm. The beam diameter was nominally 3 cm, and the annular width was 2 mm.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"13 12 1","pages":"407-410"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82650123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Spreaded-vertical-capacitor cell (SVC) for beyond 64 Mbit DRAMs 扩展垂直电容单元(SVC)用于超过64 Mbit的dram
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235353
N. Matsuo, Y. Nakata, H. Ogawa, T. Yabu, S. Matsumoto, M. Sasago, K. Hashimoto, S. Okada
{"title":"Spreaded-vertical-capacitor cell (SVC) for beyond 64 Mbit DRAMs","authors":"N. Matsuo, Y. Nakata, H. Ogawa, T. Yabu, S. Matsumoto, M. Sasago, K. Hashimoto, S. Okada","doi":"10.1109/IEDM.1991.235353","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235353","url":null,"abstract":"An advanced three-dimensionally (3-D) stacked capacitor cell, SVC, was developed. The SVC shows good electrical characteristics, and it realized a capacitance of 43 fF with a cell area of 1.8 mu m/sup 2/. The uniform formation of the capacitor-dielectric-film (oxide-nitride-oxide film: ONO) on the experimental storage electrode indicates the uniform deposition of the ONO film on all kinds of 3-D storage electrodes including that of the SVC. The SVC is the most promising cell structure for beyond 64 Mbit DRAMs (dynamic RAMs).<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"52 1","pages":"473-476"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87582732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Physical modelling of non-invasive silicon temperature measurement by infrared absorption 红外吸收非侵入式硅温度测量的物理建模
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235281
J. Sturm, C. Reaves
{"title":"Physical modelling of non-invasive silicon temperature measurement by infrared absorption","authors":"J. Sturm, C. Reaves","doi":"10.1109/IEDM.1991.235281","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235281","url":null,"abstract":"It has recently been shown that the temperature of silicon wafers can be measured in situ in rapid thermal processing reactors by monitoring the infrared absorption of the substrate at specific wavelengths. In the present work, a physical model of infrared absorption in silicon is used to determine the dominant absorption mechanisms in the relevant temperature and wavelength ranges. The model is then used to predict the ultimate temperature ranges of applicability of the technique and to show the effects of heavy doping. Since free carrier absorption dominates at wavelengths over 1.55 mu m, approximately 850 degrees C may be estimated as an upper limit for the technique of silicon temperature measurement by infrared transmission. Because bandgap absorption dominates at short wavelengths, the technique may be extended to temperatures as low as 77 K.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"2000 1","pages":"895-898"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88298226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Update of thermionic cathode progress 热离子阴极最新进展
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235373
R. Forman
{"title":"Update of thermionic cathode progress","authors":"R. Forman","doi":"10.1109/IEDM.1991.235373","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235373","url":null,"abstract":"An update of progress in programs for improving thermionic cathode devices is presented. Innovative changes in the M-type impregnated cathode, specifically, the MM, CMM, MMM and transition metal emitters designed to preserve the initial cathode surface, are discussed. Also considered are low-cost high-brightness cathodes for high-definition television (HDTV), CPD types developed in the US and scandate types in Europe and Japan. High-temperature, high-brightness cathodes (LaB/sub 6/ and transition metal carbides) for lithographic or other unique applications are also discussed. Consideration is given to low-work-function cathodes (e.g. scandate) which can deliver 1-2 A/cm/sup 2/ at a much lower temperature than conventional impregnated cathodes and are capable of delivering pulsed currents in the range of 100 A/cm/sup 2/.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"14 1","pages":"387-390"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88973160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A self-convergence erasing scheme for a simple stacked gate flash EEPROM 一种简单堆叠门闪速EEPROM的自收敛擦除方案
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235442
S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke, M. Wada
{"title":"A self-convergence erasing scheme for a simple stacked gate flash EEPROM","authors":"S. Yamada, T. Suzuki, E. Obi, M. Oshikiri, K. Naruke, M. Wada","doi":"10.1109/IEDM.1991.235442","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235442","url":null,"abstract":"A novel erasing method for simple stacked gate flash EEPROMs is described. The method makes use of avalanche hot carrier injection after erasure by Fowler-Nordheim tunneling. The threshold voltages converge to a certain 'steady-state' as a result of the injection. The steady-state is caused by a balance between avalanche hot electron injection into the floating gate and avalanche hot hole injection into the floating gate, and can be controlled easily by the channel doping. Tight distribution of threshold voltages and stable erasure without over-erased cells are demonstrated by applying cells using 0.6- mu m CMOS technology. In addition, short erase time is realized using the novel erase sequence.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"60 1","pages":"307-310"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75984077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
High speed Si PBT with buried single crystal silicide electrode by MBE MBE埋入单晶硅化电极的高速硅PBT
International Electron Devices Meeting 1991 [Technical Digest] Pub Date : 1991-12-08 DOI: 10.1109/IEDM.1991.235430
T. Ohshima, N. Nakamura, K. Nakagawa, K. Yamaguchi, M. Miyao
{"title":"High speed Si PBT with buried single crystal silicide electrode by MBE","authors":"T. Ohshima, N. Nakamura, K. Nakagawa, K. Yamaguchi, M. Miyao","doi":"10.1109/IEDM.1991.235430","DOIUrl":"https://doi.org/10.1109/IEDM.1991.235430","url":null,"abstract":"Silicon permeable base transistors (PBTs) with buried single-crystal electrodes were fabricated by developing formation techniques using molecular beam epitaxy (MBE) for obtaining single-crystal-Si/silicide/Si double-heterostructures and silicide films in submicron size patterns. A high transconductance of 50 mS/mm and high current density of 2*10/sup 4/ A/cm/sup 2/ were obtained. The highest unity current gain frequency (f/sub T/) 6 GHz. Computer simulations indicated that the value of f/sub T/ was reasonable and could be improved by more than one order of magnitude (about 120 GHz) by optimizing the device structure.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"6 4 1","pages":"33-36"},"PeriodicalIF":0.0,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77495952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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