A self-aligned pocket implantation (SPI) technology for 0,. mu m-dual gate CMOS

Abstract

A novel self-aligned pocket implantation (SPI) technology has been developed. This technology features a localized 'pocket' implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length Lg (the physical gate length) is 0.21 mu m. This process provides high punchthrough resistance and high current driving capability while maintaining low impurity concentration in the well (less than 5*10/sup 16/ cm/sup -3/). The drain junction capacitance is decreased by 30% for N-MOSFET, and by 49% for P-MOSFET, compared to conventional LDD (lightly doped drain) devices. It is found that a dual gate CMOS fabricated by the SPI technology achieves high-speed circuit performance.<>