Gate-capacitance characteristics of deep-submicron LATID (large-angle-tilt implanted drain) MOSFETs

Abstract

Gate-capacitance characteristics for LATID (large-angle-tilt implanted drain) devices are studied using high-resolution measurements and device simulation. As compared with single-S/D (source/drain), a deep-submicron LATID FET, developed to introduce sidewall spacers for reducing overlap length to approximately 0.09 mu m, is found to suppress gate-to-drain capacitance C/sub GD/ at 3.3 V operation by approximately 40%, to almost the same level as LDDs (lightly doped drains), while a LATID without spacers suffers from a >25% larger C/sub GD/. To suppress C/sub GD/, offsetting the n/sup +/ region by spacers is crucial, while the n/sup -/ region should remain fully overlapped with the gate to improve current drivability. Following this design guideline, the circuit speed of LATID can be improved by approximately 15% compared to LDDs. The deep-submicron LATID technology, with spacers, is promising for high-speed ULSI circuits.<>