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2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

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Large-scale millimeter-wave phased arrays for 5G systems 5G系统的大规模毫米波相控阵
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445432
G. Rebeiz
{"title":"Large-scale millimeter-wave phased arrays for 5G systems","authors":"G. Rebeiz","doi":"10.1109/SIRF.2016.7445432","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445432","url":null,"abstract":"The construction of large phased arrays, composed of 256-1024 elements, with relatively low-cost is one of the main problems of 5G systems. In this talk, we will present our effort in this area and show 256 element and 1024 element phased arrays operating at 60GHz. This is done using highly complex and integrated silicon (SiGe) chips, capable of phase shifting and frequency translation functions, and operation up to 100C. Measured patterns and communication links capable of 2-4 Gbps over hundreds of meters will be shown.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132017191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 200-GHz triple-push oscillator in 65-nm CMOS with design techniques for enhancing DC-to-RF efficiency 一种采用65纳米CMOS的200 ghz三推振荡器，其设计技术可提高dc - rf效率
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445473
H. Rashtian, L. Katehi, Q. Gu, X. Liu
{"title":"A 200-GHz triple-push oscillator in 65-nm CMOS with design techniques for enhancing DC-to-RF efficiency","authors":"H. Rashtian, L. Katehi, Q. Gu, X. Liu","doi":"10.1109/SIRF.2016.7445473","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445473","url":null,"abstract":"In this paper, new design techniques for improving the DC-to-RF efficiency for sub-THz triple-push oscillators in CMOS technology is presented. We investigate the effect of the bias of transistors and the impedance seen by each transistor on the overall performance of triple-push CMOS oscillators in terms of DC-to-RF efficiency. By optimizing the harmonic generation and harmonic extraction in a triple-push oscillator fabricated in 65-nm CMOS, output power of -8.75 dBm is achieved at 200-GHz while 28.8-mW of DC power is consumed. This translates into a DC-to-RF efficiency of 0.46%.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128662691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 110–132GHz VCO with 1.5dBm peak output power and 18.2% tuning range in 130nm SiGe BiCMOS for D-Band transmitters 用于d波段发射机的110-132GHz VCO，峰值输出功率为1.5dBm，调谐范围为18.2%，采用130nm SiGe BiCMOS
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445469
Sriram Muralidharan, Kefei Wu, M. Hella
{"title":"A 110–132GHz VCO with 1.5dBm peak output power and 18.2% tuning range in 130nm SiGe BiCMOS for D-Band transmitters","authors":"Sriram Muralidharan, Kefei Wu, M. Hella","doi":"10.1109/SIRF.2016.7445469","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445469","url":null,"abstract":"This paper presents the design and measurement results of a mm-wave voltage controlled oscillator in 130nm SiGe BiCMOS technology for application in D-Band transmitters. The VCO is designed using two oscillators operating at fo=60 GHz and arranged in a push-push configuration, to provide a D-Band output. The wide tuning range is achieved by employing a hyper-abrupt junction varactor. The VCO delivers a peak output power of 1.44dBm at 127GHz to a 50Ω load with a tuning range of 18.2% centered at 121GHz. The chip consumes 42mW of DC power from a 1.5V supply and hence achieves a peak DC-to-RF efficiency of 3.3%.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124850459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 130-GHz OOK transmitter in 65-nm CMOS technology 采用65纳米CMOS技术的130 ghz OOK发射机
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445484
Namhyung Kim, Heekang Son, Dong-Hyun Kim, J. Rieh
{"title":"A 130-GHz OOK transmitter in 65-nm CMOS technology","authors":"Namhyung Kim, Heekang Son, Dong-Hyun Kim, J. Rieh","doi":"10.1109/SIRF.2016.7445484","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445484","url":null,"abstract":"A 130-GHz OOK transmitter has been developed based on a 65-nm CMOS technology in this work. The transmitter is composed of a 130-GHz fundamental oscillator and a switch-based OOK modulator. The oscillator is based on an LC cross-coupled differential pair with a tapered buffer, while the switch adopts a 3-stage shunt configuration. The on/off power ratio of the switch is over 20 dB, and the transmitter exhibits an output power of -5.1 dBm with the switch turned on. The 3-dB bandwidth of the transmitter measured with a frequency domain technique is 16 GHz. The transmitter consumes 55.2 mW, mostly arising from the oscillator.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bring the system down — To a chip 把系统拆下来-拆到芯片上
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445477
S. Mohammadi
{"title":"Bring the system down — To a chip","authors":"S. Mohammadi","doi":"10.1109/SIRF.2016.7445477","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445477","url":null,"abstract":"Nanoscale CMOS Silicon on Insulator (SOI) technology is a design environment suitable for integrated circuits and systems. Watt-level stacked power amplifiers (PAs) implemented in CMOS SOI technology operating from RF to mm-wave frequencies have been demonstrated. The challenge is to improve PA efficiencies to the level achieved by GaAs and GaN technologies. CMOS SOI technology also offers a unique opportunity to implement ultra-low power circuits, integrated antennae and post-processed integrated sensors and actuators. Examples of CMOS SOI circuits and integrated devices are presented and characteristics of future single-chip systems are discussed.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130033303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 10 bit 90 MS/s SAR ADC in a 65 nm CMOS technology 一个采用65纳米CMOS技术的10位90 MS/s SAR ADC
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445483
J. Digel, M. Grozing, M. Berroth
{"title":"A 10 bit 90 MS/s SAR ADC in a 65 nm CMOS technology","authors":"J. Digel, M. Grozing, M. Berroth","doi":"10.1109/SIRF.2016.7445483","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445483","url":null,"abstract":"This paper presents a 10 bit 90 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an asynchronous conversion cycle control. The asynchronous operation allows the sampling rate to be swept over a wide range. The ADC doesn't require any external reference voltages and achieves an excellent performance without the need for calibration. The comparator uses an optimized topology which improves the decision time. At 90 MS/s, the measured effective resolution is 8.8 bit at DC and remains over 8.5 bit up to 90 MHz input frequency. With a power consumption of 1.76 mW, this results in a FoM of 44.1 fJ/conversion step. The ADC is fabricated in a 65 nm CMOS technology.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115235339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fully-integrated ultra-wideband power amplifier in CMOS Silicon on Sapphire technology 一个完全集成的超宽带功率放大器在CMOS硅蓝宝石技术
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445487
S. Helmi, Jie Cui, S. Mohammadi
{"title":"A fully-integrated ultra-wideband power amplifier in CMOS Silicon on Sapphire technology","authors":"S. Helmi, Jie Cui, S. Mohammadi","doi":"10.1109/SIRF.2016.7445487","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445487","url":null,"abstract":"A fully-integrated ultra-wideband power amplifier (PA) for multi-mode multi-band applications is designed and implemented in a standard 0.25 μm Ultra-CMOS Silicon-on-Sapphire (SOS) technology. The PA consists of two series stacked Cascode configuration to achieve high output power while maintaining stability. The PA utilizes stacked transistor switches at the input to extend the operation bandwidth without affecting its saturated output power. The PA delivers a saturated output power (PSAT) of 27 dBm (0.5 W) over a frequency range of 1.8 to 3.4 GHz with power added efficiency (PAE) and drain efficiency (DE) of higher than 20% and 29% at a supply voltage of 7 V, respectively.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116896988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CNTFET-based RF electronics — State-of-the-art and future prospects 基于cntfet的射频电子技术-现状和未来展望
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445479
M. Schroter, M. Claus, S. Hermann, J. Tittman-Otto, M. Haferlach, S. Mothes, S. Schulz
{"title":"CNTFET-based RF electronics — State-of-the-art and future prospects","authors":"M. Schroter, M. Claus, S. Hermann, J. Tittman-Otto, M. Haferlach, S. Mothes, S. Schulz","doi":"10.1109/SIRF.2016.7445479","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445479","url":null,"abstract":"Carbon nanotube (CNT) field effect transistors (FETs) are expected to have several advantages over silicon-based FETs. While most of the literature deals with digital applications, this paper gives an overview on the present status of CNTFET technology for radio-frequency analog applications, including the respective requirements. Results for transistors and circuits achieved so far as well as possible fabrication approaches for performance improvement are discussed.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125035676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Enablement of advanced silicon photonics optical passive library design leveraging silicon based RF passive development methodology 利用基于硅的射频无源开发方法实现先进的硅光子光学无源库设计
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445476
F. Ayi-Yovo, C. Durand, H. Petiton, S. Jan, F. Gianesello, D. Bucci, J. Broquin, D. Gloria
{"title":"Enablement of advanced silicon photonics optical passive library design leveraging silicon based RF passive development methodology","authors":"F. Ayi-Yovo, C. Durand, H. Petiton, S. Jan, F. Gianesello, D. Bucci, J. Broquin, D. Gloria","doi":"10.1109/SIRF.2016.7445476","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445476","url":null,"abstract":"Silicon photonics technology emerged as a promising solution to address the technical challenges related to 100 Gb/s and 400 Gb/s optical link. Enabling the development of silicon photonics products requires the development of optical passive libraries integrated within conventional CAD tools used in the CMOS design flow. The optimization and modeling of silicon photonics optical passive is therefore a key point that can be addressed by leveraging methodologies that have been previously set up for optimizing RF passive in CMOS and BiCMOS technologies. In this paper, the relevance of such an approach is evaluated: the combination of FDTD electromagnetic simulations and a Design Of Experiments (DOE) prototyping have been used for optimizing scalable Grating Couplers (GCs) targeting Wavelength-Division Multiplexing applications (WDM). The obtained models for the GC have been successfully qualified experimentally.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluation of LDMOS transistors for 10 Gbps switched mode applications and X-band power amplifier 用于10gbps开关模式应用和x波段功率放大器的LDMOS晶体管的评估
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445467
C. Wipf, R. Sorge, Jens Schmidt
{"title":"Evaluation of LDMOS transistors for 10 Gbps switched mode applications and X-band power amplifier","authors":"C. Wipf, R. Sorge, Jens Schmidt","doi":"10.1109/SIRF.2016.7445467","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445467","url":null,"abstract":"In this article we report on the capability of integrated LDMOS transistors for power amplifiers in 10 gigabit per second (Gbps) communication systems, smart power systems and X-band power amplifiers. The switched mode properties of the amplifier were evaluated using a 10.3125 Gbps pseudo random bit error sequence (PRBS) signal. A test mask according to the IEEE P802.3aq 10GBASE-LRM Ethernet standard was applied to evaluate the recorded eye diagram. No single hit was detected in the forbidden test mask regions after measuring 6 million data points. Load-pull measurements at 11 GHz show an operational gain of 16 dB, a maximum power added efficiency (PAE) of 30 % and a maximum drain efficiency (EFF) of 38 %. RF small signal scattering parameters of the LDMOS transistor were measured up to 67 GHz. A cutoff frequency of 27 GHz and a maximum oscillation frequency of 61 GHz were extracted. The investigated n-LDMOS transistor is modularly integrated into a 0.25 μm SiGe:C BiCMOS Technology.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134252396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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