A 10 bit 90 MS/s SAR ADC in a 65 nm CMOS technology

This paper presents a 10 bit 90 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an asynchronous conversion cycle control. The asynchronous operation allows the sampling rate to be swept over a wide range. The ADC doesn't require any external reference voltages and achieves an excellent performance without the need for calibration. The comparator uses an optimized topology which improves the decision time. At 90 MS/s, the measured effective resolution is 8.8 bit at DC and remains over 8.5 bit up to 90 MHz input frequency. With a power consumption of 1.76 mW, this results in a FoM of 44.1 fJ/conversion step. The ADC is fabricated in a 65 nm CMOS technology.