A 200-GHz triple-push oscillator in 65-nm CMOS with design techniques for enhancing DC-to-RF efficiency

In this paper, new design techniques for improving the DC-to-RF efficiency for sub-THz triple-push oscillators in CMOS technology is presented. We investigate the effect of the bias of transistors and the impedance seen by each transistor on the overall performance of triple-push CMOS oscillators in terms of DC-to-RF efficiency. By optimizing the harmonic generation and harmonic extraction in a triple-push oscillator fabricated in 65-nm CMOS, output power of -8.75 dBm is achieved at 200-GHz while 28.8-mW of DC power is consumed. This translates into a DC-to-RF efficiency of 0.46%.