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2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

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An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS 一种带PVT补偿的超低电压c类PMOS VCO集成电路
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2016-03-31 DOI: 10.1109/SIRF.2016.7445482
Xin Yang, Xiao Xu, T. Yoshimasu
{"title":"An ultra-low-voltage Class-C PMOS VCO IC with PVT compensation in 180-nm CMOS","authors":"Xin Yang, Xiao Xu, T. Yoshimasu","doi":"10.1109/SIRF.2016.7445482","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445482","url":null,"abstract":"A novel 2.2-GHz-band ultra-low-voltage Class-C PMOS VCO IC with negative reference and amplitude feedback loop is proposed. The negative reference initially adapts a sufficient bias for the LC-VCO circuit to ensure a robust oscillation start-up. The feedback loop then adaptively controls the bias condition of LC-VCO for Class-C operation in steady-state. The reliability of the feedback loop is enhanced over PVT variation. The Class-C VCO IC has been designed, fabricated and fully evaluated in 180-nm CMOS technology. The fabricated VCO IC exhibits a measured phase noise of -113.2 dBc/Hz at 1 MHz offset from the 2.2 GHz carrier frequency with a supply voltage of only 0.3 V.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131134720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A wideband high isolation CMOS T/R switch for X-band phased array radar systems 一种用于x波段相控阵雷达系统的宽带高隔离CMOS收发开关
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2016-01-24 DOI: 10.1109/SIRF.2016.7445470
Emre Ozeren, A. Ulku, I. Kalyoncu, Can Çalışkan, Murat Davulcu, M. Kaynak, Y. Gurbuz
{"title":"A wideband high isolation CMOS T/R switch for X-band phased array radar systems","authors":"Emre Ozeren, A. Ulku, I. Kalyoncu, Can Çalışkan, Murat Davulcu, M. Kaynak, Y. Gurbuz","doi":"10.1109/SIRF.2016.7445470","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445470","url":null,"abstract":"This paper presents an SPDT switch which is designed to operate at 8-12 GHz frequency range (X-Band), as a sub module of the front end circuit of a phased array radar. The switch distinguishes itself from its counterparts with its larger frequency range and higher isolation that is uniformly distributed over its bandwidth. It is fabricated using 0.25μm SiGe BiCMOS technology of IHP Microelectronics (Germany). As a new technique, shunt inductors are placed next to shunt transistors in order to improve trade-off between insertion loss and isolation. It has isolation higher than 30 dB in entire band, input referred 1dB compression point is 27.6 dBm, insertion loss is between 2.7-4.1 dB, input and output referred return losses are better than 11 dB in the frequency range of 8-12 GHz.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-01-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122309630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An X-band reconfigurable bandpass filter using phase change RF switches 一种使用相变射频开关的x波段可重构带通滤波器
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445462
Muzhi Wang, F. Lin, M. Rais-Zadeh
{"title":"An X-band reconfigurable bandpass filter using phase change RF switches","authors":"Muzhi Wang, F. Lin, M. Rais-Zadeh","doi":"10.1109/SIRF.2016.7445462","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445462","url":null,"abstract":"In this paper, we report on a reconfigurable bandpass filter for X-band applications. The filter is composed of coupled X/2 microstrip line resonators. Center frequency tuning of each resonator is achieved using an RF switch based on a phase change chalcogenide compound, germanium telluride, which switches in and out a loading capacitor. A combination of electric and magnetic coupling between the resonators realizes a near constant absolute-bandwidth as the filter is tuned. The center frequency of the filter is switched between 7.45 and 8.07 GHz, with a 3-dB bandwidth of ~ 500 MHz, insertion loss of less than 3.2 dB, and return loss of better than 18 dB. The measured third-order intermodulation intercept point (IIP3) and 1-dB power compression point (P1dB) are better than 30 dBm at frequency offset of 1 kHz and 25 dBm, respectively. Measured and simulated results are in good agreement. To our best knowledge, this is the first time implementation of a tunable filter using germanium telluride based phase change switches.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123210929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
0.25 μm SiGe BiCMOS 30GHz balanced vector modulator 0.25 μm SiGe BiCMOS 30GHz平衡矢量调制器
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445478
F. Tabarani, H. Schumacher
{"title":"0.25 μm SiGe BiCMOS 30GHz balanced vector modulator","authors":"F. Tabarani, H. Schumacher","doi":"10.1109/SIRF.2016.7445478","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445478","url":null,"abstract":"Vector modulators are a key component in phased array antennas and communications systems. The paper describes a novel design methodology for a bi-directional, reflection-type balanced vector modulator using metal-oxide-semiconductor field-effect (MOS) transistors as active loads, which provides an improved constellation quality. The fabricated IC occupies 787 × 1325 μm2 and exhibits a minimum transmission loss of 9 dB and return losses better than 14 dB. As an application example, its use in a 16-QAM modulator is verified.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132928358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Opportunities of Fan-out Wafer Level Packaging (FOWLP) for RF applications 面向射频应用的扇出晶圆级封装(FOWLP)的机遇
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445461
T. Braun, M. Topper, K. Becker, M. Wilke, M. Huhn, U. Maass, I. Ndip, R. Aschenbrenner, K. Lang
{"title":"Opportunities of Fan-out Wafer Level Packaging (FOWLP) for RF applications","authors":"T. Braun, M. Topper, K. Becker, M. Wilke, M. Huhn, U. Maass, I. Ndip, R. Aschenbrenner, K. Lang","doi":"10.1109/SIRF.2016.7445461","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445461","url":null,"abstract":"Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A thin film redistribution layer is applied on the reconfigured wafer routes the die pads to the space around the die on the mold compound (fan-out). After solder ball placement and package singulation by dicing a SMD compatible package is completed. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133415819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 14 dBm 110–130 GHz power amplifier and doubler chain in 90 nm SiGe BiCMOS technology 采用90 nm SiGe BiCMOS技术的14 dBm 110-130 GHz功率放大器和倍频链
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445486
R. Ben Yishay, D. Elad
{"title":"A 14 dBm 110–130 GHz power amplifier and doubler chain in 90 nm SiGe BiCMOS technology","authors":"R. Ben Yishay, D. Elad","doi":"10.1109/SIRF.2016.7445486","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445486","url":null,"abstract":"A D-Band x2 frequency multiplier-amplifier chain implemented in an advanced 90 nm SiGe BiCMOS technology is presented. The chain achieves a peak output power of 14 dBm and consists of input balun and push-push frequency doubler which drives a single-ended three stages Power Amplifier (PA). It operates from 110 GHz to 130 GHz (3 dB power bandwidth) with 5 dBm input power at V-Band and consumes a total DC power of 200 mW from a 1.6 V supply. The stand-alone doubler achieves output power >5 dBm at 110-130 GHz and occupies area of only 0.15 mm2.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
MEMS-tunable silicon-integrated cavity filters mems可调谐硅集成腔滤波器
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445460
D. Peroulis, D. Psychogiou
{"title":"MEMS-tunable silicon-integrated cavity filters","authors":"D. Peroulis, D. Psychogiou","doi":"10.1109/SIRF.2016.7445460","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445460","url":null,"abstract":"Millimeter-wave (mm-wave) frequencies (>30 GHz) are more and more occupied by new sets of applications ranging from high-data rate communication networks to security and surveillance systems. As a result, the demand for highly-versatile RF filters that are able to operate at such high frequencies and accommodate the needs of these systems is continuously increasing. A new class of mm-wave filters that are structured by silicon-integrated evanescent-mode cavity resonators and MEMS corrugated diaphragms have recently being proposed as a prospective candidate for these applications. This paper provides a general review of the attributes of this technology and its RF performance merits through various filter demonstration examples.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134598298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Microwave communication links for brain interface applications 微波通信链路的脑接口应用
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445472
L. Larson, A. Nurmikko
{"title":"Microwave communication links for brain interface applications","authors":"L. Larson, A. Nurmikko","doi":"10.1109/SIRF.2016.7445472","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445472","url":null,"abstract":"Recent experiments have demonstrated the ability of neuroscientists to gain direct access to neural signals in real time, and decode the resulting information to control various prosthetic devices. This - along with deep brain stimulation for Parkinson's disease and a variety of other conditions - extrapolates to a premise that widespread \"brain interface\" medical device technologies are a real (if long term) possibility. This paper will summarize the various approaches that have been introduced specifically to wirelessly communicate with the brain, including microelectronics technology constraints, power limits, data compression and rate issues.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125651091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Nonlinear characteristics and RF losses of CPW and TFMS lines over a wide temperature range 宽温度范围内CPW和TFMS线的非线性特性和射频损耗
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445458
K. Ben Ali, J. Raskin
{"title":"Nonlinear characteristics and RF losses of CPW and TFMS lines over a wide temperature range","authors":"K. Ben Ali, J. Raskin","doi":"10.1109/SIRF.2016.7445458","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445458","url":null,"abstract":"This paper analyzes RF losses and non-linear behavior from room temperature up to 175°C of coplanar waveguide (CPW) and thin film microstrip (TFMS) lines fabricated on both High Resistivity (HR) and Standard resistivity (STD) Silicon-on-Insulator (SOI) substrates. Through measurements it is shown that CPW topology exhibits larger 2nd harmonic distortion level, more than 25 dB higher compared with TFMS counterpart at 25°C, whereas the later shows larger insertion losses. At higher temperature, RF losses increase for both transmission line topologies whereas the 2nd and 3rd harmonic levels are almost not affected by the temperature increase.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128561476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
10.5-14.5GHz four-channel phased array receiver in 0.13-μm CMOS technology 10.5-14.5GHz四通道相控阵接收机，采用0.13 μm CMOS技术
2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 1900-01-01 DOI: 10.1109/SIRF.2016.7445468
M. Esmael, Mohamed Ayman, Karim Gooda, M. Abdalla, Mohamed Mobarak
{"title":"10.5-14.5GHz four-channel phased array receiver in 0.13-μm CMOS technology","authors":"M. Esmael, Mohamed Ayman, Karim Gooda, M. Abdalla, Mohamed Mobarak","doi":"10.1109/SIRF.2016.7445468","DOIUrl":"https://doi.org/10.1109/SIRF.2016.7445468","url":null,"abstract":"This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5-14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of -7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of 204 mW from a 1.5-V supply. This paper presents the design of all the receiver blocks; LNA, phase shifter, combiner and the I/Q mixer, and finally the layout of the full chip and post layout verification and electromagnetic simulations of entire chip are presented. The design and simulations are carried out using different CAD tools like Cadence, ADS and Sonnet.","PeriodicalId":138697,"journal":{"name":"2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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