10.5-14.5GHz four-channel phased array receiver in 0.13-μm CMOS technology

Abstract

This paper presents the design of a fully integrated CMOS 4-channel phased-array receiver for 10.5-14.5 GHz telecom infrastructure, microwave link and radar applications. The phased-array is built using 0.13μm CMOS, and has a gain of 24.5 dB at 12.5 GHz, an input IIP3 of -7.3 dBm, a NF of 4.8 dB and the RMS phase error is 3o. The chip occupies an area of 2.9×3.2mm with a total power consumption of 204 mW from a 1.5-V supply. This paper presents the design of all the receiver blocks; LNA, phase shifter, combiner and the I/Q mixer, and finally the layout of the full chip and post layout verification and electromagnetic simulations of entire chip are presented. The design and simulations are carried out using different CAD tools like Cadence, ADS and Sonnet.