{"title":"SMT evaluation for industrial and aerospace applications","authors":"G. Menozzi","doi":"10.1109/EEMTS.1988.75970","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75970","url":null,"abstract":"Work carried out in the field of surface-mount technology for aerospace, industrial, and telecommunication applications is discussed. The leadless ceramic chip carrier, a hermetic package for the -55 degrees C-to-+125 degrees C temperature range, is used in military and space applications on either ceramic or advanced printed-wiring board (PWB) interconnects. Research and development on advanced PWBs, multiplane or core structure, using copper-Invar-copper and other composite materials, is discussed. Test results are given, the current status of the technology, and the next steps of research and development are described and some aerospace applications are presented. An evaluation program which utilizes a large test structure on which mounting configurations and different component types can be evaluated is outlined.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123513497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of copper thick film for high frequency digital interconnection","authors":"E. Beyne, J. Roggen, R. Mertens","doi":"10.1109/EEMTS.1988.75946","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75946","url":null,"abstract":"Copper thick-film multilayer technology is evaluated for use as a high-frequency digital interconnect in systems with bit rates up to 600 Mb/s. To help design the interconnect, software tools which calculate the electrical parameters and performance for any two-dimensional geometry were developed and are described. The analysis is based on a quasistatic method. A thick-film multilayer test structure with high bandwidth and 50- Omega impedance was realized. The calculated line parameters show good agreement with the measured values.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131311871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Gustafsson, U. Andersson, S. Ek, L. Liljestrand
{"title":"The optimal choice of high pin count ASIC packages","authors":"K. Gustafsson, U. Andersson, S. Ek, L. Liljestrand","doi":"10.1109/EEMTS.1988.75947","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75947","url":null,"abstract":"Six different types of application-specific integrated circuit (ASIC) packages are compared with respect to production aspects, availability, reliability, thermal and electrical properties, and cost. Recommendations for the proper choice of packages for different types of applications are given. Pin-grid-array packages are found to be expensive and the through hole mounting reduces the routing capability of the board. Pad-area-array packages are a hermetic alternative with a lower price for the package as well as very good thermal and electrical properties, but they need to be mounted on expensive printed-wiring board (PWB). Another surface-mountable package which is hermetic is the ceramic leaded chip carrier with fine lead pitch. This package is even more expensive than the pin-grid array package and it is difficult to handle. It is suggested that in the future, nonhermetic alternatives will probably be dominant. Plastic quad flat pack and TapePak can be used when less than 160-170 leads are necessary, while direct assembled tape automated bonding (TAB) is believed to be the best alternative for very high pin counts.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A comparison of vapor-phase, infrared and hot-gas soldering","authors":"N. Heilmann","doi":"10.1109/EEMTS.1988.75957","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75957","url":null,"abstract":"The three most important reflow methods (vapor-phase, infrared, and hot-gas) are discussed. These methods are compared and the advantages and disadvantages of each are demonstrated. Vapor-phase and infrared are the most frequently used reflow methods. Three main reasons for using vapor-phase reflow are given: heating of printed-circuit boards and components is independent of geometry; heating is independent of package density; and the maximum achievable temperature is limited by the boiling point of the liquid used. Infrared soldering offers certain advantages which are not found in the vapor-phase process. Infrared soldering does not have such an extreme heating rate. The furnaces need much less service and create no problem with the environment.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121603432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Double-bump surface-mount technology for very high IO interconnections","authors":"F. Lovasco, M. A. Oien","doi":"10.1109/EEMTS.1988.75950","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75950","url":null,"abstract":"An area-distributed surface-mount technology that is suitable for the solder assembly of VLSI packages onto printed circuit boards is discussed. This double-bump technology entails the controlled overlapping of two molten solder bumps on both package and substrate to form a nearly cylindrical joint. A mechanical standoff is used to control the final separation between the IC package and the printed circuit board, and hence the solder joint height and shape. A simple analytical model, which provides a good understanding of the solder joint geometries which are achievable and how the joint geometry is influenced by the principal design and process parameters, was developed. This assembly technology offers several advantages. It is an evolutionary development of the well established solder-bump technology, but it provides a columnlike joint geometry and thus offers potential for better reliability and higher density. It provides a large process window because it allows for the inspection of wettability of package and substrate before assembly, and the assembly process itself involves the melting together of two molten solder surfaces. It offers the potential for the electrical inspection of hidden solder joints.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128077346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multilayer ceramic circuit boards with copper conductors","authors":"K. Nobuo, S. Aoki, Y. Imanaka, K. Niwa","doi":"10.1109/EEMTS.1988.75942","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75942","url":null,"abstract":"The application of copper (Cu) to multilayer ceramic circuit boards fabricated by the green-sheet method is studied. The glass-ceramic composite composed of borosilicate (B/sub 2/O/sub 3/-SiO/sub 2/) glass and alumina (Al/sub 2/O/sub 3/) densifies below the melting point of Cu. The major technical difficulty is to fire the circuit board without Cu oxidation and carbon residue. Carbon intermixes with the glass matrix, lowering the fired density, flexural strength, and breakdown voltage. However, less than 100 p.p.m. of carbon does not influence these properties. A 30-layer ceramic circuit board with a carbon concentration of less than 30 p.p.m. has been fabricated. The signal propagation delay time is 7.3 ns/m. The sheet resistivity of Cu conductors is 1.2 m Omega / Square Operator .<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132910512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Manufacturing implications of ultrahigh speed packaging and interconnect design","authors":"W.M. Beckenbaugh","doi":"10.1109/EEMTS.1988.75967","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75967","url":null,"abstract":"Ultra-high-speed and high-lead-count IC packaging places stringent requirements on the assembly materials and processes, interconnection technology, and physical design of products. The factory automation, testing, and information transfer requirements are also significantly increased. The impact of these requirements on interconnect media fabrication tolerances and assembly methods is discussed.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114249961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TAB, a packaging approach for VLSI technology","authors":"H. Steckhan","doi":"10.1109/EEMTS.1988.75952","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75952","url":null,"abstract":"VLSI technology is forcing semiconductor manufacturers to find innovative ways to assemble and package complex ICs for maximum reliability at minimum costs. For many performance problems, such as high number of I/O pins, mechanical stress to the chip by plastic encapsulation high logic speed and power consumption, tape automated bonding (TAB) offers a practical and cost-effective solution. The technology is demonstrated in a 10k gate array with a chip area of 145 mm/sup 2/ and a pin count of 320. The special demands of the component with respect to power dissipation and assembly requirements and their solution through the TAB technique are illustrated.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129946617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High temperature superconductors-electrical considerations and possible applications in microelectronics","authors":"R. Dumcke, G. Fotheringham, H. Reichl","doi":"10.1109/EEMTS.1988.75940","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75940","url":null,"abstract":"The impact of VLSI integration trends on the requirements of chip-to-chip interconnects is reviewed. The propagation of on-chip and off-chip interconnection systems at liquid nitrogen temperatures are discussed for signal and power lines. Material properties of high T/sub c/-superconductors are considered and the resulting changes for transmission-line properties of superconducting interconnects are pointed out. Possible applications and some open problems are discussed.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121141477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Conductor technology for high density multilayer system","authors":"M. Zorrilla","doi":"10.1109/EEMTS.1988.75945","DOIUrl":"https://doi.org/10.1109/EEMTS.1988.75945","url":null,"abstract":"Advanced high-speed, high-input/output-density integrated circuits (ICs) require model packaging techniques such as high-density multilayer polyimide-copper circuits on ceramic substrates populated with tape-automated-bonded IC chips. Thin-film techniques for pattern definition, polyimide deposition, and via etching are already well defined for multilayered modules. The compatibility of present thin-film techniques with conductor patterning methods is considered. Parametric test circuits with four metal layers have been fabricated and characterized. The minimal design rules were 25- mu m lines on 50- mu m pitch. The continuity of via chains of 20000 vias per chain was verified for 30- mu m vias on 100- mu m pitch.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134599100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}