TAB, a packaging approach for VLSI technology

Abstract

VLSI technology is forcing semiconductor manufacturers to find innovative ways to assemble and package complex ICs for maximum reliability at minimum costs. For many performance problems, such as high number of I/O pins, mechanical stress to the chip by plastic encapsulation high logic speed and power consumption, tape automated bonding (TAB) offers a practical and cost-effective solution. The technology is demonstrated in a 10k gate array with a chip area of 145 mm/sup 2/ and a pin count of 320. The special demands of the component with respect to power dissipation and assembly requirements and their solution through the TAB technique are illustrated.<>