Conductor technology for high density multilayer system

Abstract

Advanced high-speed, high-input/output-density integrated circuits (ICs) require model packaging techniques such as high-density multilayer polyimide-copper circuits on ceramic substrates populated with tape-automated-bonded IC chips. Thin-film techniques for pattern definition, polyimide deposition, and via etching are already well defined for multilayered modules. The compatibility of present thin-film techniques with conductor patterning methods is considered. Parametric test circuits with four metal layers have been fabricated and characterized. The minimal design rules were 25- mu m lines on 50- mu m pitch. The continuity of via chains of 20000 vias per chain was verified for 30- mu m vias on 100- mu m pitch.<>