{"title":"双凸点表面贴装技术,用于非常高的IO互连","authors":"F. Lovasco, M. A. Oien","doi":"10.1109/EEMTS.1988.75950","DOIUrl":null,"url":null,"abstract":"An area-distributed surface-mount technology that is suitable for the solder assembly of VLSI packages onto printed circuit boards is discussed. This double-bump technology entails the controlled overlapping of two molten solder bumps on both package and substrate to form a nearly cylindrical joint. A mechanical standoff is used to control the final separation between the IC package and the printed circuit board, and hence the solder joint height and shape. A simple analytical model, which provides a good understanding of the solder joint geometries which are achievable and how the joint geometry is influenced by the principal design and process parameters, was developed. This assembly technology offers several advantages. It is an evolutionary development of the well established solder-bump technology, but it provides a columnlike joint geometry and thus offers potential for better reliability and higher density. It provides a large process window because it allows for the inspection of wettability of package and substrate before assembly, and the assembly process itself involves the melting together of two molten solder surfaces. It offers the potential for the electrical inspection of hidden solder joints.<<ETX>>","PeriodicalId":137899,"journal":{"name":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Double-bump surface-mount technology for very high IO interconnections\",\"authors\":\"F. Lovasco, M. A. Oien\",\"doi\":\"10.1109/EEMTS.1988.75950\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An area-distributed surface-mount technology that is suitable for the solder assembly of VLSI packages onto printed circuit boards is discussed. This double-bump technology entails the controlled overlapping of two molten solder bumps on both package and substrate to form a nearly cylindrical joint. A mechanical standoff is used to control the final separation between the IC package and the printed circuit board, and hence the solder joint height and shape. A simple analytical model, which provides a good understanding of the solder joint geometries which are achievable and how the joint geometry is influenced by the principal design and process parameters, was developed. This assembly technology offers several advantages. It is an evolutionary development of the well established solder-bump technology, but it provides a columnlike joint geometry and thus offers potential for better reliability and higher density. It provides a large process window because it allows for the inspection of wettability of package and substrate before assembly, and the assembly process itself involves the melting together of two molten solder surfaces. It offers the potential for the electrical inspection of hidden solder joints.<<ETX>>\",\"PeriodicalId\":137899,\"journal\":{\"name\":\"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EEMTS.1988.75950\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Fourth IEEE/CHMT European International Electronic Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EEMTS.1988.75950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Double-bump surface-mount technology for very high IO interconnections
An area-distributed surface-mount technology that is suitable for the solder assembly of VLSI packages onto printed circuit boards is discussed. This double-bump technology entails the controlled overlapping of two molten solder bumps on both package and substrate to form a nearly cylindrical joint. A mechanical standoff is used to control the final separation between the IC package and the printed circuit board, and hence the solder joint height and shape. A simple analytical model, which provides a good understanding of the solder joint geometries which are achievable and how the joint geometry is influenced by the principal design and process parameters, was developed. This assembly technology offers several advantages. It is an evolutionary development of the well established solder-bump technology, but it provides a columnlike joint geometry and thus offers potential for better reliability and higher density. It provides a large process window because it allows for the inspection of wettability of package and substrate before assembly, and the assembly process itself involves the melting together of two molten solder surfaces. It offers the potential for the electrical inspection of hidden solder joints.<>