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2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs最新文献

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Temperature dependence of switching performance in IGBT circuits and its compact modeling IGBT电路开关性能的温度依赖性及其紧凑建模
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890812
M. Miyake, M. Ueno, J. Nakashima, H. Masuoka, U. Feldmann, H. Mattausch, M. Miura-Mattausch, T. Ogawa, T. Ueta
{"title":"Temperature dependence of switching performance in IGBT circuits and its compact modeling","authors":"M. Miyake, M. Ueno, J. Nakashima, H. Masuoka, U. Feldmann, H. Mattausch, M. Miura-Mattausch, T. Ogawa, T. Ueta","doi":"10.1109/ISPSD.2011.5890812","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890812","url":null,"abstract":"We have developed the compact IGBT model HiSIM-IGBT, based on a complete solution for the potential distribution, which connects the surface-potential of the MOS-FET part to the bipolar part by an iterative procedure in a self-consistent way. Here we report the self-heating extension of HiSIM-IGBT, a compact model for power diode including the reverse recovery effect and the model application to accurate prediction of experimental switching characteristics.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126259742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Normally-off high-voltage p-GaN gate GaN HFET with carbon-doped buffer 常关高压p-GaN栅极氮化镓HFET掺碳缓冲
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890835
O. Hilt, F. Brunner, E. Cho, A. Knauer, Eldad Bahat Treidel, J. Wurfl
{"title":"Normally-off high-voltage p-GaN gate GaN HFET with carbon-doped buffer","authors":"O. Hilt, F. Brunner, E. Cho, A. Knauer, Eldad Bahat Treidel, J. Wurfl","doi":"10.1109/ISPSD.2011.5890835","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890835","url":null,"abstract":"Normally-off GaN transistors for power applications in p-type GaN gate technology with a modified carbon-doped GaN buffer are presented. A combination of an AlGaN back-barrier with the carbon-doped buffer prevents early off-state punch-through. Simultaneously, the on-state resistance could be kept low and the threshold voltage with 1.1 V high enough for secure normally-off operation. 1000 V breakdown strength has been obtained for devices with 6 μm gate-drain spacing. The resulting breakdown scaling slope is 170 V/μm gate-drain distance. The on-state resistance is 7.4 Ωmm. The resulting VBr-to-RONA ratio (1000 V, 0.62 mΩcm2) is beyond so far reported ratios for normally-off GaN transistors. Modifications of the p-type GaN layer have shown to additionally increase the threshold voltage by 0.4 V without paying a price in the on-state resistance of the device.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128192908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
Solutions to improve flatness of Id-Vd curves of rugged nLDMOS 提高坚固型nLDMOS Id-Vd曲线平整度的解决方案
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890825
S. Mouhoubi, F. Bauwens, J. Roig, P. Gassot, P. Moens, M. Tack
{"title":"Solutions to improve flatness of Id-Vd curves of rugged nLDMOS","authors":"S. Mouhoubi, F. Bauwens, J. Roig, P. Gassot, P. Moens, M. Tack","doi":"10.1109/ISPSD.2011.5890825","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890825","url":null,"abstract":"This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Optimization of diodes using the SPEED concept and CIBH 利用SPEED概念和CIBH优化二极管
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890802
M. Pfaffenlehner, H. Felsl, F. Niedernostheide, F. Pfirsch, H. Schulze, R. Baburske, J. Lutz
{"title":"Optimization of diodes using the SPEED concept and CIBH","authors":"M. Pfaffenlehner, H. Felsl, F. Niedernostheide, F. Pfirsch, H. Schulze, R. Baburske, J. Lutz","doi":"10.1109/ISPSD.2011.5890802","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890802","url":null,"abstract":"The surge current ruggedness of free-wheeling diodes can be improved by implementing the SPEED concept (Self-adjusting P Emitter Efficiency Diode). Experiments show that the switching ruggedness of such a diode is worse than that of a conventional diode. Simulations indicate that during diode turn-off filaments are pinned at the cathode side. These filaments can be avoided by implementing CIBH (Controlled Injection of Backside Holes). It turns out that a necessary additional measure is to fully embed the p+-areas of the SPEED anode in the low-doped p-type area to avoid high electrical field strengths and current crowding at the anode side. Combining these measures, the appearance of current filaments with an extremely high current density and their pinning to a certain area in the device during the turn-off period can be avoided.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132863037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
CSTBT™(III) having wide SOA under high temperature condition CSTBT™(III)在高温条件下具有宽SOA
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890808
Y. Fukada, Kenji Suzuki, Tetsuo Takahashi, Tatsuo Harada, Hidenori Fujii, S. Ishizawa, J. Yamashita, J. Donlon, T. Terashima
{"title":"CSTBT™(III) having wide SOA under high temperature condition","authors":"Y. Fukada, Kenji Suzuki, Tetsuo Takahashi, Tatsuo Harada, Hidenori Fujii, S. Ishizawa, J. Yamashita, J. Donlon, T. Terashima","doi":"10.1109/ISPSD.2011.5890808","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890808","url":null,"abstract":"This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N<sup>+</sup> emitter width, P<sup>+</sup> diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"308 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132669523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reliability study of Au-In transient liquid phase bonding for SiC power semiconductor packaging SiC功率半导体封装中Au-In瞬态液相键合的可靠性研究
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890840
B. Grummel, H. Mustain, Z. Shen, A. Hefner
{"title":"Reliability study of Au-In transient liquid phase bonding for SiC power semiconductor packaging","authors":"B. Grummel, H. Mustain, Z. Shen, A. Hefner","doi":"10.1109/ISPSD.2011.5890840","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890840","url":null,"abstract":"Transient liquid phase (TLP) bonding is a promising advanced die-attach technique for wide-bandgap power semiconductor and high-temperature packaging. TLP bonding advances modern soldering techniques by raising the melting point to over 500 °C without detrimental high-lead materials. The bond also has greater reliability and rigidity due in part to a bonding temperature of 200 °C that drastically lowers the peak bond stresses. Furthermore, the thermal conductivity is fractionally increased 67 % while the bond thickness is substantially reduced, lowering the thermal resistance by an order of magnitude or more. It is observed that Au-In TLP bonds exude excellent electrical reliability against thermal cycling degradation if designed properly as experimentally confirmed in this work.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124577233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Development of the next generation 1700V trench-gate FS-IGBT 下一代1700V沟栅FS-IGBT的研制
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890788
Y. Onozawa, D. Ozaki, H. Nakano, T. Yamazaki, N. Fujishima
{"title":"Development of the next generation 1700V trench-gate FS-IGBT","authors":"Y. Onozawa, D. Ozaki, H. Nakano, T. Yamazaki, N. Fujishima","doi":"10.1109/ISPSD.2011.5890788","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890788","url":null,"abstract":"This paper describes the next generation 1700V trench-gate FS-IGBT utilized the micro p-base structure for the first time. The new 1700V IGBT has been achieved that “better turn-on di/dt controllability”, “oscillation free turn-off” and “improved Von-Eoff trade-off relationship” as well as 600V and 1200V IGBTs. Furthermore, the critical thermal runaway temperature has successfully been elevated by the newly developed field-stop layer, which leads to increase of maximum junction temperature as high as 175 deg. C.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology 高性能Pch-LDMOS晶体管，宽电压范围从35V到200V SOI LDMOS平台技术
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890786
S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada
{"title":"High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology","authors":"S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada","doi":"10.1109/ISPSD.2011.5890786","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890786","url":null,"abstract":"We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122128390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Interface charge trapping and hot carrier reliability in high voltage SOI SJ LDMOSFET 高压SOI SJ LDMOSFET的界面电荷俘获与热载流子可靠性
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890859
M. Antoniou, F. Udrea, E. Tee, Y. Hao, S. Pilkington, Kee Kia Yaw, D. K. Pal, A. Hoelke
{"title":"Interface charge trapping and hot carrier reliability in high voltage SOI SJ LDMOSFET","authors":"M. Antoniou, F. Udrea, E. Tee, Y. Hao, S. Pilkington, Kee Kia Yaw, D. K. Pal, A. Hoelke","doi":"10.1109/ISPSD.2011.5890859","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890859","url":null,"abstract":"This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models. The introduction of the SJ structure in the drift region of the LDMOSFET allows a shorter length and significantly higher drift doping both of which result in very low on-state resistance for a given breakdown voltage 170V. However careful design and optimization of the Super-junction layers is needed to avoid the combined effects of parastic JFET effect, impact ionization and charge trapping. The paper discusses these complex phenomena and gives solutions to increase robustness against instability problems.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129785947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
0.25μm, 20V high performance complementary bipolar transistor with dual EPI and oxide-filled deep trench isolation for high frequency DC-DC converters 0.25μm, 20V高性能互补双极晶体管，具有双EPI和氧化物填充深沟槽隔离，用于高频DC-DC转换器
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890818
T. Kwon, S. Haynie, A. Sadovnikov, P. Allard, J. Strout, A. Strachan
{"title":"0.25μm, 20V high performance complementary bipolar transistor with dual EPI and oxide-filled deep trench isolation for high frequency DC-DC converters","authors":"T. Kwon, S. Haynie, A. Sadovnikov, P. Allard, J. Strout, A. Strachan","doi":"10.1109/ISPSD.2011.5890818","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890818","url":null,"abstract":"Power supply designers must increase the switching frequency of converters to meet industry demands for small sizes. In order to handle high switching frequency, a closed-loop DC-DC converter needs a high-speed error amplifier with low Rdson.Qg LDMOS power switches. In this paper, 0.25um, 20V high performance complementary bipolar transistors were developed for the high-speed error amplifier design. Dual epi was used to suppress parasitic bipolar behavior that leads to a latch-up. Also, an oxide-filled deep trench isolation was used to minimize parasitic capacitance. As a result, robust 5GHz NPN and 3GHz PNP transistors were integrated with a low Rdson.Qg LDMOS.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128527010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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