高性能Pch-LDMOS晶体管,宽电压范围从35V到200V SOI LDMOS平台技术

S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada
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引用次数: 15

摘要

我们开发了高性能的Pch-LDMOS晶体管,额定电压范围从35V到200V SOI LDMOS平台技术。通过采用一种新颖的沟道结构,在200V Pch-LDMOS晶体管中实现了172 μA/μm的高饱和漏极电流,与Nch-LDMOS晶体管相当。在保持- 240和- 284 V的高导通和关断击穿电压的同时,获得了3470 mΩ * mm2的低导通电阻。同时,通过对结构和场极板的优化设计,证明了35V ~ 200V LDMOS晶体管具有较好的低导通电阻性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology
We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.
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