S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada
{"title":"高性能Pch-LDMOS晶体管,宽电压范围从35V到200V SOI LDMOS平台技术","authors":"S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada","doi":"10.1109/ISPSD.2011.5890786","DOIUrl":null,"url":null,"abstract":"We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"132 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology\",\"authors\":\"S. Shimamoto, Y. Yanagida, S. Shirakawa, K. Miyakoshi, T. Imai, T. Oshima, J. Sakano, S. Wada\",\"doi\":\"10.1109/ISPSD.2011.5890786\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.\",\"PeriodicalId\":132504,\"journal\":{\"name\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"132 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2011.5890786\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2011.5890786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology
We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.