Solutions to improve flatness of Id-Vd curves of rugged nLDMOS

Abstract

This work summarizes results of TCAD simulations aiming to reduce/suppress the bump in the output characteristics of rugged nLDMOS devices. It is shown that the origin of the bump is not due to bipolar activation. Thus, by simple variations of the geometrical parameters and/or process variations, the intrinsic MOS of the nLDMOS could be driven in a regime allowing a drastic improvement of its Id-Vd flatness with limited impact on the sRon-Vbd trade-off.