Y. Fukada, Kenji Suzuki, Tetsuo Takahashi, Tatsuo Harada, Hidenori Fujii, S. Ishizawa, J. Yamashita, J. Donlon, T. Terashima
{"title":"CSTBT™(III)在高温条件下具有宽SOA","authors":"Y. Fukada, Kenji Suzuki, Tetsuo Takahashi, Tatsuo Harada, Hidenori Fujii, S. Ishizawa, J. Yamashita, J. Donlon, T. Terashima","doi":"10.1109/ISPSD.2011.5890808","DOIUrl":null,"url":null,"abstract":"This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N<sup>+</sup> emitter width, P<sup>+</sup> diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"308 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"CSTBT™(III) having wide SOA under high temperature condition\",\"authors\":\"Y. Fukada, Kenji Suzuki, Tetsuo Takahashi, Tatsuo Harada, Hidenori Fujii, S. Ishizawa, J. Yamashita, J. Donlon, T. Terashima\",\"doi\":\"10.1109/ISPSD.2011.5890808\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N<sup>+</sup> emitter width, P<sup>+</sup> diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.\",\"PeriodicalId\":132504,\"journal\":{\"name\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"308 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2011.5890808\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2011.5890808","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CSTBT™(III) having wide SOA under high temperature condition
This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N+ emitter width, P+ diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.