R. Rudolf, C. Wagner, L. O'Riain, K. Gebhardt, B. Kuhn-Heinrich, B. von Ehrenwall, A. von Ehrenwall, M. Strasser, M. Stecher, U. Glaser, S. Aresu, P. Kuepper, A. Mayerhofer
{"title":"Automotive 130 nm smart-power-technology including embedded flash functionality","authors":"R. Rudolf, C. Wagner, L. O'Riain, K. Gebhardt, B. Kuhn-Heinrich, B. von Ehrenwall, A. von Ehrenwall, M. Strasser, M. Stecher, U. Glaser, S. Aresu, P. Kuepper, A. Mayerhofer","doi":"10.1109/ISPSD.2011.5890780","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890780","url":null,"abstract":"In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129913389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiyong Lim, O. Seok, Young-shil Kim, M. Han, Minki Kim
{"title":"A new vertical GaN SBD employing in-situ metallic gallium ohmic contact","authors":"Jiyong Lim, O. Seok, Young-shil Kim, M. Han, Minki Kim","doi":"10.1109/ISPSD.2011.5890837","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890837","url":null,"abstract":"We proposed and fabricated new vertical GaN Schottky barrier diodes (SBDs) employing in-situ metallic gallium (Ga) ohmic contacts which increase the forward current of a vertical GaN SBD considerably. Highly conductive metallic Ga was formed in-situ at the bottom of n+ GaN substrate due to a high thermal budget during n-epi layer growth so that the ohmic contact was well-formed due to the metallic Ga. The forward current density of the proposed device was 625 A/cm2 at 2 V while that of the conventional device was 300 A/cm2. We also employed the floating metal ring and field plate to achieve the high breakdown voltage. The breakdown voltage of the proposed and conventional device was 880 V and 850 V respectively.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hidemoto Tomita, H. Eguchi, Shinya Kijima, Norihiro Honda, Tetsuya Yamada, H. Yamawaki, H. Aoki, K. Hamada
{"title":"Wide-voltage SOI-BiCDMOS technology for high-temperature automotive applications","authors":"Hidemoto Tomita, H. Eguchi, Shinya Kijima, Norihiro Honda, Tetsuya Yamada, H. Yamawaki, H. Aoki, K. Hamada","doi":"10.1109/ISPSD.2011.5890782","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890782","url":null,"abstract":"This paper describes a new wide-voltage SOI-BiCDMOS technology for high-temperature automotive applications. This technology is capable of integrating 35V, 60V, and 80V Nch and Pch LDMOS, 35V BJT, and 6V CMOS devices on a single chip. The devices are completely isolated dielectrically using both deep trench isolation (DTI) and a buried oxide (BOX) layer in a silicon-on-insulator (SOI) wafer for stable operation at high temperatures up to 175°C. The devices were developed using a 0.35μm process. In particular, the LDMOS devices have achieved competitive levels of low Ron∗ A and good SOA.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jian-Hsing Lee, T. Kao, C. Chan, Jin-Lian Su, H. Su, Kuo-Cheng Chang
{"title":"The ESD failure mechanism of ultra-HV 700V LDMOS","authors":"Jian-Hsing Lee, T. Kao, C. Chan, Jin-Lian Su, H. Su, Kuo-Cheng Chang","doi":"10.1109/ISPSD.2011.5890822","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890822","url":null,"abstract":"A new kind of ESD failure mechanism is found in the UHV 700V LDNMOS during the HBM ESD zapping event. The device is damaged by its own charges and board stored charges, not damaged by the HBM stress current. The device junction capacitor and test-board capacitor store the charges from the ESD tester before the avalanche breakdown occurring. After the avalanche breakdown, the two capacitors discharge the stored charges to give the additional currents to stress the device. This phenomenon is called the charged-capacitor model (CCM) [1].","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123753977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SiC power devices — Present status, applications and future perspective","authors":"M. Ostling, R. Ghandi, C. Zetterling","doi":"10.1109/ISPSD.2011.5890778","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890778","url":null,"abstract":"Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Recently Schottky diodes are offered by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now available on the commercial market. The interest is rapidly growing for these devices in high power and high temperature applications. The main advantages of wide bandgap semiconductors are their very high critical electric field capability. From a power device perspective the high critical field strength can be used to design switching devices with much lower losses than conventional silicon based devices both for on-state losses and reduced switching losses. This paper reviews the current state of the art in active switching device performance for both SiC and GaN. SiC material quality and epitaxy processes have greatly improved and degradation free 100 mm wafers are readily available. The SiC wafer roadmap looks very favorable as volume production takes off. For GaN materials the main application area is geared towards the lower power rating level up to 1 kV on mostly lateral FET designs. Power module demonstrations are beginning to appear in scientific reports and real applications. A short review is therefore given. Other advantages of SiC is the possibility of high temperature operation (> 300 °C) and in radiation hard environments, which could offer considerable system advantages.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128043381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
So Watanabe, M. Mori, Taiga Arai, K. Ishibashi, Y. Toyoda, T. Oda, T. Harada, K. Saito
{"title":"1.7kV trench IGBT with deep and separate floating p-layer designed for low loss, low EMI noise, and high reliability","authors":"So Watanabe, M. Mori, Taiga Arai, K. Ishibashi, Y. Toyoda, T. Oda, T. Harada, K. Saito","doi":"10.1109/ISPSD.2011.5890787","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890787","url":null,"abstract":"A novel 1.7kV IGBT with deep floating-p layers separated from trench gates has been developed to realize low loss, low EMI noise, and high reliability. Separating floating-p layers from the trench gates reduces excess V<inf>GE</inf> overshoot, which results in a 51% smaller reverse recovery dV<inf>AK</inf>/dt than the conventional IGBT. The deep floating p-layers weaken the electric field under the trenches, which results in an avalanche breakdown voltage of 2250V. In addition, the E<inf>on</inf> + E<inf>off</inf> for the proposed structure can be reduced by 47% more than that of the conventional one, maintaining a low V<inf>CE(sat)</inf> of 2.3V at 125°C.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"132 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114004643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Celaya, A. Saxena, S. Saha, V. Vashchenko, K. Goebel
{"title":"Prognostics of power MOSFET","authors":"J. Celaya, A. Saxena, S. Saha, V. Vashchenko, K. Goebel","doi":"10.1109/ISPSD.2011.5890815","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890815","url":null,"abstract":"This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and Gaussian process regression to perform prognostics. The approach is validated with experiments on 100V power MOSFETs. The failure mechanism for the stress conditions is determined to be die-attachment degradation. Change in ON-state resistance is used as a precursor of failure due to its dependence on junction temperature. The experimental data is augmented with a finite element analysis simulation that is based on a two-transistor model. The simulation assists in the interpretation of the degradation phenomena and SOA (safe operation area) change.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131564409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise
{"title":"Full understanding of hot-carrier-induced degradation in STI-based LDMOS transistors in the impact-ionization operating regime","authors":"S. Poli, S. Reggiani, G. Baccarani, E. Gnani, A. Gnudi, M. Denison, S. Pendharkar, R. Wise","doi":"10.1109/ISPSD.2011.5890813","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890813","url":null,"abstract":"Hot-carrier-injection (HCI) effects are studied in n-channel rugged LDMOS transistors in high current-voltage biases, by monitoring the linear and saturation regimes. Experimental data reveal that the degradation effects responsible for the HCI parameter drifts are mainly localized in the channel and in the drift region close to the drain. The temperature dependence of the HCI degradation is analyzed to gain understanding in the underlying physics. TCAD simulations aimed at investigating the sensitivity of the current shift to different local distributions of trapped charges have been carried out, and a compact model for the linear current has been developed for the purpose of extracting the effective-mobility degradation in the channel and the charge trapped in the drift region. The overall methodology represents a new approach to the HCI analysis suitable for device structures with STI in the drain extension region.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132928650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Storasta, Munaf T. A. Rahimo, M. Bellini, A. Kopta, U. Vemulapati, N. Kaminski
{"title":"The radial layout design concept for the Bi-mode insulated gate transistor","authors":"L. Storasta, Munaf T. A. Rahimo, M. Bellini, A. Kopta, U. Vemulapati, N. Kaminski","doi":"10.1109/ISPSD.2011.5890789","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890789","url":null,"abstract":"In this paper we present a new radial design concept for an optimized layout of anode shorts in the Bi-mode Insulating Gate Transistor (BiGT). The study shows that the arrangement of the n+-stripes plays a key role for the on-state characteristics of the BiGT. With the aid of 3D device simulations the visualization of the plasma distribution during the on-state conduction was obtained in a 0.25 × 4 mm2 large BiGT model area. The influence of the dimensioning and layout of the anode shorts was simulated and compared with measured on-state curves. A clear improvement of plasma distribution in the device when the stripes are arranged orthogonally (radially) to the pilot-IGBT boundary is observed in 3D simulations. Measurements confirm lower on-state losses as a result of better utilization of the device area.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134287067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Integrated low power and high bandwidth optical isolator for monolithic power MOSFETs driver","authors":"N. Rouger, J. Crebier, O. Lesaint","doi":"10.1109/ISPSD.2011.5890864","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890864","url":null,"abstract":"An integrated solution for the galvanic isolation between power transistors and their control unit is presented in this paper. This solution is based on a monolithic integration of a photodetector within a power MOSFET without any modification of its fabrication process. This photoreceiver can be associated with a monolithic driver to drive high side switches. Exhaustive characteristics for several integrated photodetectors are presented and discussed: quantum efficiency, step response, small signal analysis and sensitivity to the High Voltage MOSFET's Drain. The results of this analysis are photoreceivers with a Full Width at Half Maximum above 300MHz and a responsivity above 0.15A/W at a wavelength of 500nm. This leads to an integrated low power and high bandwidth optical isolation.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133376932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}