2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs最新文献_第4页

GaN based Super HFETs over 700V using the polarization junction concept 基于氮化镓的700V以上超高压场效应管采用极化结概念

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890845

A. Nakajima, M. H. Dhyani, E. Narayanan, Y. Sumida, H. Kawai

引用次数: 15

Improvement of switching trade-off characteristics between noise and loss in high voltage MOSFETs 高压mosfet中噪声与损耗之间开关权衡特性的改进

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890854

W. Saito, S. Aida, S. Koduki, M. Izumisawa

引用次数: 4

A novel power system in package with 3D chip on chip interconnections of the power transistor and its gate driver 一种新型的功率晶体管与栅极驱动器片上三维互连的封装电源系统

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890857

S. Timothe, R. Nicolas, Crebier Jean-Christophe, Gaude Victor, Irène Pheng

引用次数: 4

Investigation on wirebond-less power module structure with high-density packaging and high reliability 高密度封装、高可靠性的无线连接电源模块结构研究

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890843

Y. Ikeda, Y. Iizuka, Y. Hinata, M. Horio, M. Hori, Yoshikazu Takahashi

引用次数: 45

A versatile 30V analog CMOS process in a 0.18μm technology for power management application 用于电源管理应用的0.18μm技术的通用30V模拟CMOS工艺

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890830

Yong-Keon Choi, I. Park, H. Lim, Mi-Young Kim, Chul-Jin Yoon, Nam-Joo Kim, K. Yoo, L. Hutter

引用次数: 7

Thermal impedance spectroscopy of power modules during power cycling 电源模块在电源循环过程中的热阻抗谱

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890841

Alexander Henlser, D. Wingert, C. Herold, J. Lutz, M. Thoben

引用次数: 14

Avalanche instability in oxide charge balanced power MOSFETs 氧化物电荷平衡功率mosfet的雪崩不稳定性

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890814

J. Yedinak, R. Stokes, D. Probst, S. Kim, A. Challa, S. Sapp

引用次数: 10

Opportunities and challenges with net zero energy buildings 净零能耗建筑的机遇与挑战

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890776

Satyen Mukherjee

{"title":"Opportunities and challenges with net zero energy buildings","authors":"Satyen Mukherjee","doi":"10.1109/ISPSD.2011.5890776","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890776","url":null,"abstract":"Buildings represent around 41% of the total energy consumption in the US followed closely by industry (31%) and transportation (28%). One of the milestones set by the US Department of Energy is the development and deployment of net zero energy buildings defined as buildings that on a yearly average spend as much energy as they generate using renewable energy sources. Realization of net zero energy buildings require a wide ranges of technologies, systems and solutions with varying degrees of complexity and sophistication depending upon the location and surrounding environmental conditions. Lighting is a dominant load in buildings followed by heating, cooling, ventilation and various plug loads. This paper will address the roles of different technologies, devices and control strategies being developed for low energy buildings leading to net zero energy buildings. These include high efficiency lighting, daylight integration, DC power bus, solar power integration; closed loop integrated control, smart grid interface as well as emerging approaches such as chilled beams and active facades. All of these involve power conversion and controls in one form or the other where high voltage or high power integrated solutions are key to commercial viability. In addition to this, the role of whole building modeling and simulation in the development and deployment of the solutions will be addressed.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128073502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A novel normally-off GaN power tunnel junction FET 一种新型的常关断GaN功率隧道结场效应管

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890844

Li Yuan, Hongwei Chen, Qi Zhou, Chunhua Zhou, K. J. Chen

引用次数: 8

P-type isolated GGNMOS with a deep current path for ESD protection p型隔离型GGNMOS具有用于ESD保护的深电流路径

2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890870

J. Yoo, Jong-Min Kim, J. Byeon, Young-Sang Son, Jae-Young Park, W. Jung

{"title":"P-type isolated GGNMOS with a deep current path for ESD protection","authors":"J. Yoo, Jong-Min Kim, J. Byeon, Young-Sang Son, Jae-Young Park, W. Jung","doi":"10.1109/ISPSD.2011.5890870","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890870","url":null,"abstract":"In this paper, we propose a P-type Isolated GGNMOS (PI-GGNMOS) with a deep current path to improve holding voltage (Vh) of Electro-Static Discharge (ESD) protection device. In order to make the deep current path under the channel, the proposed ESD protection device has a p-type stud between source and the channel, compared to the conventional GGNMOS (Gate-Grounded NMOS). To verify the performance of the proposed structure, we simulated and measured the test structure that is fabricated in a 0.35μm Bipolar-CMOS-DMOS (BCD) process. We found that the proposed structure improves the holding voltage from 6.4V to 8.48V for 5V GGNMOS at 5.3μm pitch. In case of conventional 7V GGNMOS at 7.0μm pitch, the holding voltage is 8.7V. Therefore, we can use 5V PI-GGNMOS as a 7V ESD protection device with 32 % pitch reduction compared to conventional 7V ESD device without any additional process. The actual size of ESD cell is saved by 42.3%, considering It2. This improvement is attributed to the p-type stud which reduces gain and extends effective base width of parasitic NPN in GGNMOS. Consequently, the PI-GGNMOS can apply for upper range ESD protection at same cost.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131795022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5