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2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs最新文献

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5kV class 4H-SiC PiN diode with low voltage overshoot during forward recovery for high frequency inverter 5kV级4H-SiC引脚二极管，用于高频逆变器正向恢复时电压过调
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890849
S. Ogata, Y. Miyanagi, K. Nakayama, A. Tanaka, K. Asano
{"title":"5kV class 4H-SiC PiN diode with low voltage overshoot during forward recovery for high frequency inverter","authors":"S. Ogata, Y. Miyanagi, K. Nakayama, A. Tanaka, K. Asano","doi":"10.1109/ISPSD.2011.5890849","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890849","url":null,"abstract":"Forward recovery characteristics have been reported in a 5 kV class SiC pin diode used for a high frequency inverter. The 5 kV class SiC pin diode obviously has low forward voltage overshoot and an extremely small voltage shift along with a higher forward current increase rate or junction temperature as compared to the Si fast diode. The minority carrier lifetime has also been evaluated from the forward recovery characteristics, and its dependence on temperature has been investigated. Next, the relation between the minority carrier lifetime and the forward voltage drop were investigated. Even at a higher junction temperature, it was confirmed that the calculated relations between the drift region thickness and the ambipolar diffusion length approximated the best values to maintain low forward voltage drop.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128294349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
SKiN: Double side sintering technology for new packages SKiN:用于新包装的双面烧结技术
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890856
T. Stockmeier, P. Beckedahl, C. Gobl, Thomas Malzer
{"title":"SKiN: Double side sintering technology for new packages","authors":"T. Stockmeier, P. Beckedahl, C. Gobl, Thomas Malzer","doi":"10.1109/ISPSD.2011.5890856","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890856","url":null,"abstract":"SKiN technology comprises the sintering of power chips to a substrate (i.e. DBC), a top side sintering of the power chips to a flexible circuit board, and the sintering of the substrate to a pin-fin heat sink. The resulting power device has a very low volume and weight and demonstrates unprecedented thermal, electrical, and reliability performance. Therefore, this technology is ideally suited to provide better power electronic solutions for a range of applications, i.e. electric vehicles, renewable energies and variable speed motor drives. The process to manufacture a 400 Amp, 600 V Dual IGBT, sintered to an aluminum pin-fin heat sink will be described in detail and electrical, thermal and reliability results will be shown.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133274709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
Limits of strongly punch-through designed IGBTs 强穿透设计igbt的极限
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890800
T. Raker, H. Felsl, F. Niedernostheide, F. Pfirsch, H. Schulze
{"title":"Limits of strongly punch-through designed IGBTs","authors":"T. Raker, H. Felsl, F. Niedernostheide, F. Pfirsch, H. Schulze","doi":"10.1109/ISPSD.2011.5890800","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890800","url":null,"abstract":"We will focus on the turn-off behavior of strongly punch-through designed field-stop IGBTs. Our numerical simulations with a monolithic multi-cell structure show that the appearance of current filaments may limit the safe operating area (SOA) of very thin devices with a high resistivity of base material [1]. A detailed analysis of current densities and electric field distributions gives insight into the mechanisms resulting in the formation of current filaments. The limit for a filament-free turn-off behavior can be found in the thickness-vs.-resistivity phase diagram. It could be shown that also other device parameters, such as field-stop and p-emitter design, highly influence susceptibility for the appearance of current filaments during the turn-off phase.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114250477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip 集成在CMOS栅极驱动芯片中的信号绝缘无芯变压器的设计与特性
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890865
S. Timothe, R. Nicolas, Crebier Jean-Christophe, Arnould Jean-Daniel
{"title":"Design and characterization of a signal insulation coreless transformer integrated in a CMOS gate driver chip","authors":"S. Timothe, R. Nicolas, Crebier Jean-Christophe, Arnould Jean-Daniel","doi":"10.1109/ISPSD.2011.5890865","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890865","url":null,"abstract":"With the development of multi-level, multiphase or network converters requiring the implementation of numerous distinct power transistor gate drivers, the control signal insulation is becoming more and more important in power converters. This paper presents an isolation technique based on a coreless transformer integrated in a CMOS silicon die together with the gate driver and other required functions. The associated demodulation circuit will also be presented, as the control signal must be modulated at a high frequency through the coreless transformer. The chosen design methodology will be explained and experimental results will be shown in order to validate the functionality.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114972127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
4H-SiC bipolar junction transistors with record current gains of 257 on (0001) and 335 on (000–1) 4H-SiC双极结晶体管，记录电流增益为257(0001)和335 (000-1)
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890848
H. Miyake, T. Kimoto, J. Suda
{"title":"4H-SiC bipolar junction transistors with record current gains of 257 on (0001) and 335 on (000–1)","authors":"H. Miyake, T. Kimoto, J. Suda","doi":"10.1109/ISPSD.2011.5890848","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890848","url":null,"abstract":"We demonstrate 4H-SiC bipolar junction transistors (BJTs) with record current gains. Improved current gain was achieved by utilizing optimized device geometry as well as optimized surface passivation and continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. Current gain (β) of 257 was achieved for 4H-SiC BJTs fabricated on the (0001)Si-face. The gain of 257 is twice as large as the previous record gain. We also demonstrate, for the first time, BJTs on the (000–1)C-face that showed the highest β of 335 among the SiC BJTs ever reported.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122282898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS 高压NLDMOS中寄生BJT导通增强两级漏极饱和电流的研究
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890827
Chih-Chang Cheng, H. Chou, F. Y. Chu, R. Liou, Y. Lin, K. Wu, Y. Jong, C. Tsai, J. Cai, H. Tuan
{"title":"Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS","authors":"Chih-Chang Cheng, H. Chou, F. Y. Chu, R. Liou, Y. Lin, K. Wu, Y. Jong, C. Tsai, J. Cai, H. Tuan","doi":"10.1109/ISPSD.2011.5890827","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890827","url":null,"abstract":"A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121046446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Novel high voltage LDMOS on partial SOI with double-sided charge trenches 基于部分SOI的新型高压LDMOS
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890794
X. Luo, Y. G. Wang, T. Lei, L. Lei, D. Fu, G. Yao, M. Qiao, Bo Zhang, Zhaoji Li
{"title":"Novel high voltage LDMOS on partial SOI with double-sided charge trenches","authors":"X. Luo, Y. G. Wang, T. Lei, L. Lei, D. Fu, G. Yao, M. Qiao, Bo Zhang, Zhaoji Li","doi":"10.1109/ISPSD.2011.5890794","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890794","url":null,"abstract":"A novel partial silicon-on-insulator (PSOI) high-voltage LDMOS is proposed and its breakdown mechanism is investigated numerically and experimentally. The PSOI LDMOS features double-sided charge trenches on the top and bottom interfaces of the buried oxide (BOX) (DTPSOI). In high-voltage blocking state, the charges located in the trenches enhance the electric field strength in the BOX, and a Si window makes the substrate share the vertical voltage drop and modulates the lateral field in the SOI layer. Both increase the blocking voltage (BV). A BV>700V DTPSOI LDMOS is realized on a 8μm-thick SOI layer over the 1.2μm BOX and 1.5μm-deep trench. Moreover, the Si window alleviates the self-heating effect.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122863630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Ultrathin 400V FS IGBT for HEV applications 用于HEV应用的超薄400V FS IGBT
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890791
Heike Boving, T. Laska, A. Pugatschow, W. Jakobi
{"title":"Ultrathin 400V FS IGBT for HEV applications","authors":"Heike Boving, T. Laska, A. Pugatschow, W. Jakobi","doi":"10.1109/ISPSD.2011.5890791","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890791","url":null,"abstract":"400V IGBT and freewheeling diode as well based on 40μm thin wafer technology have been developed for electric and hybrid electric vehicles with a DC link voltage of 120V to 200V. First prototype ultrathin devices worldwide showed clearly reduced overall losses since both on state and switching losses are directly dependent on the chip thickness. The new 40μm chips also exhibited a very high dI/dt during switching resulting in high voltage overshoots exceeding the maximum allowed breakdown voltage of 400V. For this reason an overall stray inductance as small as possible is required to make use of the fast switching behavior of the new devices. Optimization of the switching behavior of both IGBT and Diode could be obtained by adapting dI/dt to an overall stray inductance of 33nH but still with reduced losses at the same time. On state voltage of both IGBT and Diode could be decreased by about 200mV. Turn off energy loss could be decreased by 10%, total losses of IGBT and Diode during turn on could be reduced by about 10% in comparison to standard 650V devices","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125614037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Electro-thermal instability in multi-cellular Trench-IGBTs in avalanche condition: Experiments and simulations 雪崩条件下多细胞沟- igbt的电热不稳定性:实验与模拟
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890806
M. Riccio, A. Irace, G. Breglio, P. Spirito, E. Napoli, Y. Mizuno
{"title":"Electro-thermal instability in multi-cellular Trench-IGBTs in avalanche condition: Experiments and simulations","authors":"M. Riccio, A. Irace, G. Breglio, P. Spirito, E. Napoli, Y. Mizuno","doi":"10.1109/ISPSD.2011.5890806","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890806","url":null,"abstract":"This paper reports on the results of a study on electro-thermal instability induced in multi-cellular Trench-IGBTs in avalanche condition. Experimental measurements, made on T-IGBTs, show possible inhomogeneous current distribution under Unclamped Inductive Switching (UIS) confirmed by transient infrared thermography measurements. Together with this, an analytical modeling of avalanche behavior has been included in a compact electro-thermal simulator to study the interaction between a large numbers of elementary cells of T-IGBTs forced in avalanche condition. Electro-thermal simulations qualitatively replicate the possible inhomogeneous operation observed experimentally. Finally a possible theoretical interpretation of the instability in avalanche condition for T-IGBT is given.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133082844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Reliability and performance optimization of 42V N-channel drift MOS transistor in advanced BCD technology 先进BCD技术下42V n沟道漂移MOS晶体管的可靠性和性能优化
2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs Pub Date : 2011-05-23 DOI: 10.1109/ISPSD.2011.5890860
A. Molfese, P. Gattari, G. Marchesi, G. Croce, G. Pizzo, F. Alagi, F. Borella
{"title":"Reliability and performance optimization of 42V N-channel drift MOS transistor in advanced BCD technology","authors":"A. Molfese, P. Gattari, G. Marchesi, G. Croce, G. Pizzo, F. Alagi, F. Borella","doi":"10.1109/ISPSD.2011.5890860","DOIUrl":"https://doi.org/10.1109/ISPSD.2011.5890860","url":null,"abstract":"Optimization flow for a 42V N-channel drift MOS in an advanced BCD technology in terms of performance and stability is described. The origin of the very fast on state resistance (Ron) degradation detected during reliability tests under off state on the starting device has been identified in borderless silicon nitride used as stop layer during contact etch. The final solution including a process step introduction, device geometry modification and drain doping profile optimization improves performance and addresses both voltage capability and reliability requirements.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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