Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS

Abstract

A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.