Chih-Chang Cheng, H. Chou, F. Y. Chu, R. Liou, Y. Lin, K. Wu, Y. Jong, C. Tsai, J. Cai, H. Tuan
{"title":"高压NLDMOS中寄生BJT导通增强两级漏极饱和电流的研究","authors":"Chih-Chang Cheng, H. Chou, F. Y. Chu, R. Liou, Y. Lin, K. Wu, Y. Jong, C. Tsai, J. Cai, H. Tuan","doi":"10.1109/ISPSD.2011.5890827","DOIUrl":null,"url":null,"abstract":"A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.","PeriodicalId":132504,"journal":{"name":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS\",\"authors\":\"Chih-Chang Cheng, H. Chou, F. Y. Chu, R. Liou, Y. Lin, K. Wu, Y. Jong, C. Tsai, J. Cai, H. Tuan\",\"doi\":\"10.1109/ISPSD.2011.5890827\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.\",\"PeriodicalId\":132504,\"journal\":{\"name\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2011.5890827\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2011.5890827","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS
A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.
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