CSTBT™(III) having wide SOA under high temperature condition

Abstract

This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N⁺ emitter width, P⁺ diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off failure.