1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon最新文献_第2页

The emergence of stacked 3D silicon and its impact on microelectronics systems integration 叠层三维硅的出现及其对微电子系统集成的影响

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552405

J. Carson

{"title":"The emergence of stacked 3D silicon and its impact on microelectronics systems integration","authors":"J. Carson","doi":"10.1109/ICISS.1996.552405","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552405","url":null,"abstract":"Stacked 3D silicon has been under development for a number of years at a substantial level of investment on the part of Government as well as public and private investors. Volume manufacturing of this technology is now in place and foundry services are provided to designers of Stacked 3D silicon components and products. Stacked 3D silicon has already had a major impact on microelectronics systems and products into which it has been integrated. Examples given include solid state data recorders, digital signal processors, massively parallel processors, artificial neural networks, imaging processing, and imaging sensors. Manufacturing and cost issues are identified and discussed along with present status and projections showing that, as volumes rise, no significant premium will be required to incorporate Stacked 3D Silicon into standard products. The performance advantages of Stacked 3D silicon are very large: the ultra-high scale density results in factors of hundreds to thousands in both speed and power when ICs are designed for 3D. The paper concludes with a picture of the coming next generation 3D stacked silicon: 10-1000 layers of ultra-thin, low power circuits with 1000s of inter-layer interconnect comprising entire systems in a single cube.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121942993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A current-mode sense amplifier for low voltage non-volatile memories 一种用于低压非易失性存储器的电流模式感测放大器

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552421

C. Calligaro, P. Rolandi, N. Telecco, G. Torelli

引用次数: 7

Feasible regions quantify the probabilistic configuration power of arrays with multiple fault types 可行域量化了具有多种故障类型的阵列的概率配置功率

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552437

L. LaForge

引用次数: 4

A 16.6 cm/sup 2/ large area integrated circuit consisting of 9 video signal processors 一个16.6 cm/sup /的大面积集成电路，由9个视频信号处理器组成

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552418

J. Otterstedt, M. Kuboschek, J. Castagne, J. Mucha

{"title":"A 16.6 cm/sup 2/ large area integrated circuit consisting of 9 video signal processors","authors":"J. Otterstedt, M. Kuboschek, J. Castagne, J. Mucha","doi":"10.1109/ICISS.1996.552418","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552418","url":null,"abstract":"In this paper we introduce a large area integrated circuit (LAIC) called MAXPE9 which integrates 9 programmable video signal processing elements (PEs) on an area of 16.6 cm/sup 2/. Each PE has a peak arithmetic performance of 1 giga operations per second (GOPS). Due to yield considerations redundancy concepts have been implemented that even in the presence of production defects result in working chips utilizing a lower number of PEs. Each PE has built in self-test (BIST) capabilities which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PEs are switched off. Only the PEs passing the BIST are used for video processing tasks. Furthermore, the global input and output buses can be reconfigured using arrays of laser fuses and laser links, thus circumventing defects which are otherwise lethal for the complete chip. Prototypes have been fabricated in a 0.8 /spl mu/m CMOS process structured by masks using wafer stepping with overlapping exposures. Employing the redundancy, on these prototypes up to 6 PEs per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS per chip for video coding tasks (like H.261, MPEG-1 and MPEG-2).","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134488643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

CostAS-KGD process cost modeling 成本- kgd过程成本建模

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552438

D. Ammann, A. Thiel, C. Habiger, G. Troster

引用次数: 3

Survey of low power techniques for VLSI design VLSI设计中的低功耗技术综述

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552423

E. de Angel, E. Swartzlander

引用次数: 10

Laser reconfiguration for yield enhancement of a 16.6 cm/sup 2/ monolithic multiprocessor system 16.6 cm/sup /单片多处理器系统成品率提高的激光重构

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552417

H. Schroder, T. Hillmann-Ruge, J. Otterstedt

{"title":"Laser reconfiguration for yield enhancement of a 16.6 cm/sup 2/ monolithic multiprocessor system","authors":"H. Schroder, T. Hillmann-Ruge, J. Otterstedt","doi":"10.1109/ICISS.1996.552417","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552417","url":null,"abstract":"A 16.6 cm/sup 2/ monolithic large area integrated multiprocessor system comprising 9 identical programmable video signal processing elements was reconfigured by excimer laser formed connections and discontinuities of conductor lines in a redundant bus system. The yield enhancement of functional processors amounts to 13.3%. On two prototypes, the laser reconfiguration of the bus system led to 4 functional processors per chip at 66 MHz, providing a peak arithmetic performance of 4 GOPS per multiprocessor system. The power supply to defective processors with a high stand-by power consumption was terminated by laser, leading to a halving of power consumption. Furthermore, for the improvement of the laser process, vertical links between two metallization levels were formed on two chips with different standard CMOS layer sequences on special test structures. For the yield statistics of the formed vertical links, a contact resistance R/sub K/>3 /spl Omega/ was treated as a failure. With the laser processing of vertical links with an area of 14/spl times/14 /spl mu/m/sup 2/, a yield of 100% has been achieved. Beyond those, conventional accelerated life time tests were performed to examine the reliability of laser formed vertical links. An extrapolation of Black's equation to operating conditions (100/spl deg/C, 2.5 mA) resulted in a failure rate of 0.1% in 39 years.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124861779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules 多芯片模块上高速数字电路的低开销嵌入式高速测试方案

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552428

C. Maier, H. Greub, B. Philhower, S. Steidl, A. Garg, M. Ernest, S. Carlough, P. Campbell, J. McDonald

引用次数: 4

Fast yield prediction for accurate costing of ICs 快速良率预测，精确成本集成电路

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552435

G. A. Allan, A. J. Walton

引用次数: 1

Testability analysis of pipelined data paths 流水线数据路径的可测试性分析

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552433

G. Buonanno, Fabrizio Ferrandi, D. Sciuto

引用次数: 0