1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon最新文献

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Testability and signal integrity in a low cost multichip module 低成本多芯片模块的可测试性和信号完整性
A. Omer, A. Flint
{"title":"Testability and signal integrity in a low cost multichip module","authors":"A. Omer, A. Flint","doi":"10.1109/ICISS.1996.552426","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552426","url":null,"abstract":"The design process for low-cost multichip modules is presented. Modifications to the design are often made in order to increase testability. Some of these modifications can degrade signal integrity, however. The important aspects to consider in order to make rational design tradeoffs are presented.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115662962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A wafer-scale MEMS and analog VLSI system for active drag reduction 一种用于主动减阻的晶圆级MEMS和模拟VLSI系统
B. Gupta, R. Goodman, F. Jiang, T. Tsao, Y. Tai, S. Tung, Chih-Ming Ho
{"title":"A wafer-scale MEMS and analog VLSI system for active drag reduction","authors":"B. Gupta, R. Goodman, F. Jiang, T. Tsao, Y. Tai, S. Tung, Chih-Ming Ho","doi":"10.1109/ICISS.1996.552410","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552410","url":null,"abstract":"We describe an analog CMOS VLSI system that can process real-time signals from integrated shear stress sensors to detect regions of high shear stress along a surface in an airflow. The outputs of the CMOS circuit control the actuation of integrated micromachined flaps with the goal of reducing this high shear stress on the surface and thereby lowering the total drag. We have designed, fabricated, and tested components of this system in a wind tunnel in both laminar and turbulent flow regimes with the goal of building a wafer-scale system.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132177712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A VLSI inner product macrocell VLSI内积宏单元
L. Breveglieri, L. Dadda
{"title":"A VLSI inner product macrocell","authors":"L. Breveglieri, L. Dadda","doi":"10.1109/ICISS.1996.552408","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552408","url":null,"abstract":"Microcontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic DSP computations may be too inefficient when computed by software on the core CPU of the microcontroller. The architecture of a VLSI macrocell, for the ST9 microcontroller (8 bit), dedicated to the computation of the inner (scalar) product of two vectors of integer numbers and based on the multiply and accumulate algorithm, is here defined and developed. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimised so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128433503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A programmable processing element dedicated as building block for a large area integrated multiprocessor system 用于大面积集成多处理器系统的可编程处理元件
K. Hermann, J. Hilgenstock, K. Gaedke, H. Jeschke, P. Pirsch
{"title":"A programmable processing element dedicated as building block for a large area integrated multiprocessor system","authors":"K. Hermann, J. Hilgenstock, K. Gaedke, H. Jeschke, P. Pirsch","doi":"10.1109/ICISS.1996.552416","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552416","url":null,"abstract":"The architecture and implementation of a programmable processing element dedicated as building block for a large area integrated multiprocessor system is presented. The processor element allows an efficient implementation of video coding standards. It consists of a RISC processor supplemented by a low level coprocessor for computation intensive convolution-like tasks. Several of the processing elements can be bus-connected to built a coarse-grained MIMD based large area integrated multiprocessor system. Each of the processor elements provides high performance for video coding tasks in order to keep the overall number of required processing elements for complex real-time video coding applications small. A key feature of the processing element to support large area integration is a unidirectional data supply which allows reconfiguration strategies for the interconnection network. Furthermore on-chip program and data memories have been implemented in order to relax the overall bandwidth requirements of the large area integrated multiprocessor system.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Use of multi-port memories in programmable structures for architectural synthesis 多端口存储器在可编程结构中的应用
C. Mandal, R. M. Zimmer
{"title":"Use of multi-port memories in programmable structures for architectural synthesis","authors":"C. Mandal, R. M. Zimmer","doi":"10.1109/ICISS.1996.552441","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552441","url":null,"abstract":"In this paper we make a study of the capabilities required of memories to support the synthesis of designs using structured architectures. We explore the advantages of using multi-port memories with two write ports as an architectural component over conventional memories with a single write port in such a synthesis environment. A study the of the memory resources available in some of the current Field Programmable Gate Arrays (FPGA) is made. We then propose a multi-port memory structure that could be suitable for use in programmable structures such as FPGAs, to facilitate implementations of designs through HLS. The principal advantages of the proposed memory structure are its flexibility, simplicity and its ability to support more efficient execution of operations than existing memory structures.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116731485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A VLSI architecture for an 80 Gb/s ATM switch core 80gb /s ATM交换核心的VLSI架构
P. Andersson, C. Svensson
{"title":"A VLSI architecture for an 80 Gb/s ATM switch core","authors":"P. Andersson, C. Svensson","doi":"10.1109/ICISS.1996.552406","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552406","url":null,"abstract":"A new ATM switch core architecture for single chip implementation is proposed The two main constraints, I/O capacity and buffer memory capacity are addressed by combining the speed capability of bipolar and the complexity capability of CMOS in a BiCMOS process. A single chip throughput of 8*10 Gb/s with very low cell loss (through a large shared buffer) is anticipated.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"153 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132434704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A conceptual analysis framework for low power design of embedded systems 嵌入式系统低功耗设计的概念分析框架
W. Fornaciari, P. Gubian, D. Sciuto, Cristina Silvano
{"title":"A conceptual analysis framework for low power design of embedded systems","authors":"W. Fornaciari, P. Gubian, D. Sciuto, Cristina Silvano","doi":"10.1109/ICISS.1996.552424","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552424","url":null,"abstract":"The recent growing demand for portable computing and personal communication applications combined with the continuous increment of integration level and operating frequency of VLSI circuits, contributed to increase the importance of power dissipation issues in electronic systems. Most of the available low power design and estimation techniques provides optimization during the last phases of an integrated circuit design, i.e. gate, circuit and layout level. The issue of low power techniques and estimation is almost completely ignored above the gate level. An analysis methodology operating at Register Transfer Level (RTL) is a key factor to obtain early estimation results, while maintaining an acceptable level of accuracy in the results. The goal is to provide the designer the capability of analyzing different solutions in the architectural design space, before proceeding with the synthesis tasks. The aim of this paper is to provide an analysis framework targeting accurate and efficient estimation of power dissipation in embedded systems at RTL level. The proposed model combines the reduced complexity of the RTL description with the accuracy of the gate level description.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122410891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
MCM-L as a cost-effective solution for high-speed digital design MCM-L是一种经济高效的高速数字设计解决方案
A. Thiel, C. Habiger, G. Troster
{"title":"MCM-L as a cost-effective solution for high-speed digital design","authors":"A. Thiel, C. Habiger, G. Troster","doi":"10.1109/ICISS.1996.552440","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552440","url":null,"abstract":"Laminated multi-chip-module technology (MCM-L) is well known for its cost effectiveness in large-volume applications. However, the implementation of advanced designs such as RF-analog or high-speed digital circuits suffers mainly from the large dielectric losses of the organic dielectric layers, conductor losses, and the manufacturing tolerances of state-of-the-art MCM-L technologies. However, if MCM-L substrate behaviour could be modelled and simulated more accurately, these drawbacks could be overcome. Indeed, the basis of accurate simulation results are precise electrical models of the interconnect. In this paper a theoretical analysis of typical MCM-L interconnects and measurements on MCM-L buildups are presented. Based on the measurement results, obtained mainly by TDR/TDT setups, it is demonstrated how MCM-L substrates can be a cost-effective solution for high-speed designs.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122839986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Microelectromechanical probe for an integrated electroantennographic system 集成天线系统的微机电探头
B. Ghodsian, M. Syrzycki, G. Gries, M. Parameswaran
{"title":"Microelectromechanical probe for an integrated electroantennographic system","authors":"B. Ghodsian, M. Syrzycki, G. Gries, M. Parameswaran","doi":"10.1109/ICISS.1996.552415","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552415","url":null,"abstract":"A microelectromechanical system (MEMS) probe for a miniaturized integrated system based on an electroantennographic technique is being developed for isolating and amplifying the nerve impulses that are superimposed on the receptor potential of a single sensillum hair on the insect's antenna. The ultimate aim of this work is to integrate this system onto a single silicon substrate, using both silicon surface micromachining technology and hybrid assembly techniques. The entire system comprises of two components: (a) a microelectromechanical probe; and (b) an ultra-low input bias current amplifier. Two types of probes have been developed. One based on the surface micromachining technology with an electrostatic actuation mechanism and the other one based on a simple glass capillary technique. These probes have been hybrid integrated with the ultra-low input bias current amplifier. The surface micromachined probe aims at penetrating its sharp polysilicon tip (cross-section of 2 by 2 /spl mu/m) into the base of sensillum hair to detect the nerve impulses, whereas the glass capillary works by placing it above an already cut-off tip of a sensillum hair. Here, the authors report on the results of their investigation on developing an appropriate design for the probe to be used in an integrated system which explores the potential use of the insect antenna as a biological sensor for pheromone study. The authors also show the selectivity and sensitivity of these biological sensors as compared to the one currently used in a conventional gas chromatography system.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117342202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Yield analysis of a novel scheme for defect-tolerant memories 一种新的容错记忆方案的良率分析
I. Koren, Z. Koren
{"title":"Yield analysis of a novel scheme for defect-tolerant memories","authors":"I. Koren, Z. Koren","doi":"10.1109/ICISS.1996.552434","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552434","url":null,"abstract":"The recent increases in the size of memory ICs have made designers realize that there exists a need for new defect-tolerance techniques, since the traditional methods are no longer effective. One such new technique, the Flexible Multi-Macro (FMM) technique has recently been suggested and implemented in a 1 Gb DRAM circuit. In this paper we present a yield analysis of the FMM design and compare its yield to that of the most common defect-tolerance technique of adding spare rows and columns to the memory array.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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