80gb /s ATM交换核心的VLSI架构

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI:10.1109/ICISS.1996.552406

P. Andersson, C. Svensson

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引用次数: 20

摘要

在BiCMOS工艺中，结合双极的速度能力和CMOS的复杂度能力，解决了I/O容量和缓冲存储器容量这两个主要制约因素。预计单芯片吞吐量为8* 10gb /s，单元损耗非常低(通过大型共享缓冲区)。

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A VLSI architecture for an 80 Gb/s ATM switch core

A new ATM switch core architecture for single chip implementation is proposed The two main constraints, I/O capacity and buffer memory capacity are addressed by combining the speed capability of bipolar and the complexity capability of CMOS in a BiCMOS process. A single chip throughput of 8*10 Gb/s with very low cell loss (through a large shared buffer) is anticipated.

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来源期刊

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

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