A VLSI inner product macrocell

Abstract

Microcontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic DSP computations may be too inefficient when computed by software on the core CPU of the microcontroller. The architecture of a VLSI macrocell, for the ST9 microcontroller (8 bit), dedicated to the computation of the inner (scalar) product of two vectors of integer numbers and based on the multiply and accumulate algorithm, is here defined and developed. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimised so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated.