VLSI设计中的低功耗技术综述

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI:10.1109/ICISS.1996.552423

E. de Angel, E. Swartzlander

{"title":"VLSI设计中的低功耗技术综述","authors":"E. de Angel, E. Swartzlander","doi":"10.1109/ICISS.1996.552423","DOIUrl":null,"url":null,"abstract":"This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"9 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Survey of low power techniques for VLSI design\",\"authors\":\"E. de Angel, E. Swartzlander\",\"doi\":\"10.1109/ICISS.1996.552423\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.\",\"PeriodicalId\":131620,\"journal\":{\"name\":\"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon\",\"volume\":\"9 5\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICISS.1996.552423\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICISS.1996.552423","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

本文综述了数字电路的低功耗技术。本文所提出的技术已在改进型布斯乘法器中实现。以0.6 /spl mu/m的工艺设计了倍增器，并在PowerMill中进行了仿真。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Survey of low power techniques for VLSI design

This paper presents a survey of low power techniques for digital circuits. The techniques presented in this paper have been implemented in modified-Booth multipliers. The multipliers have been designed in 0.6 /spl mu/m technology and simulated in PowerMill.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

自引率

0.00%

发文量