Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

Abstract

The difficulty of cost-effectively identifying Known Good Die (KGD) is increased in circuits requiring multiple die packaged in Multi-Chip Modules (MCMs). Such circuits typically have high frequency I/O signals which are difficult to measure using inexpensive test equipment. The cost of full Built-In Self-Test (BIST) can be prohibitive, particularly when device integration levels are low. This paper presents a scheme for testing die for functionality and speed at minimal cost. The scheme also allows testing of MCM traces and testing of on-chip circuits both before and after packaging. The scheme was developed for use in Rensselaer Polytechnic Institute's F-RISC/G 1 ns processor project.