Fast yield prediction for accurate costing of ICs

Abstract

The paper reports an efficient method to determine the cost of manufacturing an IC based on estimates of its manufacturability. A large number of small samples of the device layout are used to estimate the critical area and hence the manufacturability of the device as a whole. The accuracy of these estimates is comparable to those obtained from a full extraction but uses only a fraction of the resources. The critical area is extracted using efficient O(n log n) polygon based algorithms that are not restricted to Manhattan style layouts and are therefore capable of processing commercial device layouts. The tool has been used successfully on a number of large industrial designs.