Feasible regions quantify the probabilistic configuration power of arrays with multiple fault types

Abstract

The bulk of results for the performance of configuration architectures treat the case of failed processor, but neglect switches that are stuck open or closed. By contrast, the present work characterizes this multivariate problem in the presence of either independent and identically distributed (iid) or clustered faults. Suppose that the designer wishes to assure, with high probability, a fault-free s/spl times/t array. If local sparing is used then, as we report, the resulting area is (i) /spl Theta/(st log st) in the presence of faulty elements or faulty elements and switches stuck open; (ii) /spl Theta/(st log/sup 2/ st) in the presence of faulty elements and switches stuck closed; (iii) /spl Theta/([st]/sup 2/ log st) in the presence of faulty elements and switches that may be either stuck open or stuck closed. We also furnish bounds on maximum wirelength and an optimal configuration algorithm.