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1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon最新文献

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Tradeoffs in chip and substrate complexity and cost for field programmable multichip modules 现场可编程多芯片模块在芯片和衬底复杂性和成本上的权衡
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552429
J. Darnauer, W. Dai
{"title":"Tradeoffs in chip and substrate complexity and cost for field programmable multichip modules","authors":"J. Darnauer, W. Dai","doi":"10.1109/ICISS.1996.552429","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552429","url":null,"abstract":"Field programmable MCMs (FPMCMs) can be used to improve the cost-effectiveness of large logic emulation and reconfigurable computing systems. In this paper, we consider two MCM-D based FPMCMs developed at UCSC to illustrate the impact of chip size on substrate wiring density and module cost. We then present a simple model of an idealized FPMCM that can be used to generate relative cost and yield estimates for different architectures. Architectural implications of this model are presented including the optimal number of chips, effect of chip bonding technology on overall cost, and limits to the integration factor for MCMs. We then briefly consider how increasing CMOS density, and innovative technologies like chip-on-chip and chip stacking might affect substrate density in the near future.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114786087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Array-based testing of FPGAs: architecture and complexity 基于阵列的fpga测试:架构和复杂性
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552432
W. Huang, F. Meyer, F. Lombardi
{"title":"Array-based testing of FPGAs: architecture and complexity","authors":"W. Huang, F. Meyer, F. Lombardi","doi":"10.1109/ICISS.1996.552432","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552432","url":null,"abstract":"This paper analyzes the architectural and complexity features of the array-based testing technique for field programmable gate arrays (FPGAs). The analysis is pursued using a hybrid (functional/stuck-at) single fault model by considering both the architecture of the configurable logic block (CLB) as well as the whole FPGA. Its evaluation using three commercially available FPGA families by Xilinx is presented in detail; emphasis is given to the different array configurations which permit the observability/controllability requirements of the testing process to satisfy the input/output restrictions (given by the I/O pins) of the FPGA, while still reducing the number of required programming phases.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Reconfiguration and yield for TESH: a new hierarchical interconnection network for 3-D integration TESH的重构与成品率:一种新的三维集成层次互联网络
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552436
V. K. Jain, T. Ghirmai, S. Horiguchi
{"title":"Reconfiguration and yield for TESH: a new hierarchical interconnection network for 3-D integration","authors":"V. K. Jain, T. Ghirmai, S. Horiguchi","doi":"10.1109/ICISS.1996.552436","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552436","url":null,"abstract":"This paper presents the reconfiguration and yield of a new interconnection network, \"Tori connected mESHes (TESH)\". Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors, it permits efficient VLSI/ULSI realization, and it appears to be well suited for 3-D VLSI/ULSI implementation. This is due in part to the fact that it requires far fewer number of vertical wires than most other multi-computer networks of comparable diameter, as demonstrated by a 4096 node example. Presented in the paper are the architecture of the new network, node addressing and message routing, VLSI/ULSI considerations, and most importantly, the reconfiguration and yield studies. Also very briefly discussed are the mappings on to the network of some applications.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Optoelectronic multichip modules based on microoptoelectromechanical system fabrication techniques 基于微机电系统制造技术的光电多芯片模块
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552411
Seungug Koh, C. Ahn, H.J. Garter, D. Sadler, A. Cook
{"title":"Optoelectronic multichip modules based on microoptoelectromechanical system fabrication techniques","authors":"Seungug Koh, C. Ahn, H.J. Garter, D. Sadler, A. Cook","doi":"10.1109/ICISS.1996.552411","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552411","url":null,"abstract":"The improvements of communication delay and connectivity by optical interconnection links and multichip module packaging indicate that optoelectronic multichip modules (OE-MCMs) utilizing both technologies will appear in computer systems and communication networks in the near future. However OE-MCM implementation requires seamless integration of electronic and photonic devices and interconnection networks as well as availability of reliable components. In this paper, innovative device structures and fabrication strategies for OE-MCMs are proposed such that they can be fabricated in a batch mode by a well-established IC fabrication process without causing any fabrication compatibility problems. The proposed OE-MCMs utilize three different technologies (optoelectronic interconnection, multichip module packaging, and MEMS fabrication technologies) at the module level and thereby create microoptoelectromechanical systems (MOEMS) which are smart microstructures of photonic, electronic, and mechanical devices and components. This paper addresses the feasibility of the proposed MOEMS through fabrication, assembly, and characterization of OE-MCM prototypes.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The quasi-Booth multiplier 准布斯乘数
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552409
L. Dadda, V. Piuri, F. Salice
{"title":"The quasi-Booth multiplier","authors":"L. Dadda, V. Piuri, F. Salice","doi":"10.1109/ICISS.1996.552409","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552409","url":null,"abstract":"A new approach to number representation is presented to implement fast parallel multipliers: the operands are given in a signed-digit representation, similar to the one proposed by Booth. With respect to a multiplier based on the Booth's notation, our approach allows one to save circuit complexity and, as a consequence, silicon area (up to 20% for the partial product generator).","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130500006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reconfigurable analog integrated circuit architecture based on switched-capacitor techniques 基于开关电容技术的可重构模拟集成电路结构
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552422
E.K.F. Lee
{"title":"Reconfigurable analog integrated circuit architecture based on switched-capacitor techniques","authors":"E.K.F. Lee","doi":"10.1109/ICISS.1996.552422","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552422","url":null,"abstract":"A reconfigurable analog integrated circuit architecture based on switched-capacitor techniques is proposed. The architecture consists of an array of opamps and programmable capacitor arrays (PCAs) interconnected by an interconnection network. The routing switches in the interconnection networks not only function as interconnection switches but also switches for charge transfer. This scheme minimizes the number of routing switches and the settling time of the embedded circuits. The architecture is also highly flexible and allows the implementation of various circuits including different types of data converters.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"366 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115472252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI architecture of a scalable matrix transposer 一种可扩展矩阵转置器的VLSI架构
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552445
O. Fatemi, S. Panchanathan
{"title":"VLSI architecture of a scalable matrix transposer","authors":"O. Fatemi, S. Panchanathan","doi":"10.1109/ICISS.1996.552445","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552445","url":null,"abstract":"In this paper, we present an ASIC implementation of matrix transposition (MT) using FPGA. MT is an important operation in 2-dimensional signal and image processing applications. Recently several parallel and pipelined architectures for real-time implementation of MT have been presented in the literature. However these implementations are not scalable. For example an architecture for the transposition of an 8/spl times/8 matrix cannot be directly obtained from a 4/spl times/4 implementation. We propose a parallel and pipelined architecture for real-time MT. This architecture is modular and cascadable. In addition it has a small execution time and low communication complexity.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124883731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Towards an integrated sub-nanogram mass measurement system 迈向集成亚纳克质量测量系统
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552413
B. Ghodsian, J. Chen, M. Parameswaran, M. Syrzycki
{"title":"Towards an integrated sub-nanogram mass measurement system","authors":"B. Ghodsian, J. Chen, M. Parameswaran, M. Syrzycki","doi":"10.1109/ICISS.1996.552413","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552413","url":null,"abstract":"This paper reports on developing the working prototype of a miniaturized mass measurement system for measurements of object's mass in the range of nanograms, in liquid and gaseous environments, using commercially available CMOS-compatible micromachining technology. When used in liquid environment, the device will be able to determine bio-masses of biological cells. The entire system will comprise of a four components, that will be integrated onto a single silicon substrate, using silicon CMOS-compatible micromachining technology and hybrid assembly technique: (a) micromachined resonant structures for mass measurement, (b) resonance sensors with associated electronics circuitry, (c) micromachined planar coil, (d) miniaturized electromagnet device.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127379038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance analysis of a 10-Gbit/s digital switch on MCM MCM上10gbit /s数字开关性能分析
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552431
C. Truzzi, E. Beyne, E. Ringoot
{"title":"Performance analysis of a 10-Gbit/s digital switch on MCM","authors":"C. Truzzi, E. Beyne, E. Ringoot","doi":"10.1109/ICISS.1996.552431","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552431","url":null,"abstract":"The paper describes a test device realised as an MCM including four identical unencapsulated ASICs mounted on a 5-layer thin-film substrate. The MCM is a 12.8 Gbit/sec data switch and it has been designed with the purpose of performance evaluation of the module interconnection technology. A validation methodology has been developed to highlight the effect of variables such as line properties, switching noise, crosstalk and buffer topologies on the signal integrity. This approach has been used to characterise the transmission rate of the digital switch and to evaluate the system performance of the interconnection technology.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multichip module yield enhancement using passive substrate fault tolerance 采用无源基板容错技术提高多芯片模块良率
1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI: 10.1109/ICISS.1996.552427
C. Peacock, H. Bolouri, C. Habiger
{"title":"Multichip module yield enhancement using passive substrate fault tolerance","authors":"C. Peacock, H. Bolouri, C. Habiger","doi":"10.1109/ICISS.1996.552427","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552427","url":null,"abstract":"The widespread use of multichip module (MCM) technology is currently restricted by high substrate cost, poor substrate yield and low quality level of mounted components: the known good die (KGD) problem. This paper examines three yield enhancing fault tolerance techniques suitable for use with conventional (passive) substrates with the aid of a generic processor-memory MCM architecture. The use of spare memory dies and a paged address space is shown to be a very effective solution to the KGD problem for this particular architecture.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"66 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132443021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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