准布斯乘数

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon Pub Date : 1996-10-09 DOI:10.1109/ICISS.1996.552409

L. Dadda, V. Piuri, F. Salice

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引用次数: 0

摘要

提出了一种新的数字表示方法来实现快速并行乘法器:操作数以类似于Booth提出的符号数字表示形式给出。关于基于布斯符号的乘法器，我们的方法允许人们节省电路复杂性，因此，硅面积(部分产品发生器高达20%)。

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The quasi-Booth multiplier

A new approach to number representation is presented to implement fast parallel multipliers: the operands are given in a signed-digit representation, similar to the one proposed by Booth. With respect to a multiplier based on the Booth's notation, our approach allows one to save circuit complexity and, as a consequence, silicon area (up to 20% for the partial product generator).

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1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon

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