V. Gupta, M. Parameswaran, L. Goldenberg, J. McEwen
{"title":"Toward the development of a non-invasive pressure-flow sensor system for the detection of prostate cancer in men","authors":"V. Gupta, M. Parameswaran, L. Goldenberg, J. McEwen","doi":"10.1109/ICISS.1996.552414","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552414","url":null,"abstract":"The fabrication of a pressure and flow sensor together on a single silicon substrate is presented. The detection of prostate cancer using this pressure-flow sensor system is explained. The flow sensor is based on well known thermal anemometer principles. The change in the piezoresistance due to stress being the pressure sensing principle. The realization process of the sensor is described. A pressure-flow study has been performed to characterize the sensor. Simple circuits are used to nullify the cross-talk between pressure and flow measurement.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133790627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Kolesar, C. Dyson, R. Reston, R. Fitch, D. G. Ford, S.D. Nelms
{"title":"Tactile integrated circuit sensor realized with a piezoelectric polymer","authors":"E. Kolesar, C. Dyson, R. Reston, R. Fitch, D. G. Ford, S.D. Nelms","doi":"10.1109/ICISS.1996.552444","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552444","url":null,"abstract":"A two-dimensional, electrically-multiplexed tactile sensor was realized by coupling a piezoelectric polyvinylidene fluoride (PVDF) polymer film to a monolithic silicon integrated circuit (IC). The IC incorporates 64 sensor electrodes arranged in a symmetrical 8/spl times/8 matrix. Each electrode occupies a 400/spl times/400 /spl mu/m square area, and they are separated from each other by 300 /spl mu/m. A 40-/spl mu/m thick piezoelectric PVDF polymer film was attached to the electrode array with a non-conductive urethane adhesive. The response of the tactile sensor is linear for loads spanning 0.8 to 135 grams-of-force (gmf) (0.008-1.35 Newtons (N)). The time required to electrically interrogate, measure, and record the response of the sensor's set of 64 taxels is less than 50 ms, the hysteresis level is tolerable, and, for operation in the sensor's linear range, taxel crosstalk is negligible. The historically persistent stability and response reproducibility limitations associated with piezoelectric-based tactile sensors have been resolved by implementing a pre-charge voltage bias technique to establish known pre- and post-load sensor responses. A rudimentary tactile object image measurement procedure has been devised to recognize the silhouette of a sharp edge, square, trapezoid, isosceles triangle, circle, toroid, slotted screw, and cross-slotted screw.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"54 27","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114005975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reduced complexity SIMD-class architectures","authors":"M. A. Glover, A. Rucinski, W. Miller","doi":"10.1109/ICISS.1996.552442","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552442","url":null,"abstract":"System engineering applied in leading microelectronic technologies requires novel computing architectures. These architectural counterparts of emerging technologies are expected to be dramatically different from existing architectural paradigms. To address this need, we are introducing a class of architectures which maintain computing robustness and reduced complexity in the interconnect domain, and still substantially differ from well established systolic systems. A class representative, a DRAM based system, is described in detail, with a permutation generation as an example of application.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127951529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SOM (self-organizing map) implemented by wafer scale integration-its self-organizing behavior under defects","authors":"M. Yasunaga, I. Hachiya","doi":"10.1109/ICISS.1996.552439","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552439","url":null,"abstract":"Self-Organizing Map (SOM) implemented by Wafer Scale Integration (WSI) will provide us very-high-speed and desk-top-size hardware for practical applications. Thanks to a synergistic effect of all neurons for ordering, the SOM-WSI is expected to reach the desired global-ordering-state permitting defective neurons in it. In this paper, we mathematically evaluated the robustness of the SOM against defective neurons. Furthermore, experiments on the defective SOM were carried out and the results agreed well with the theoretical ones. From these evaluations, high fault-tolerance of the present neuro-computer has been shown. The results and the criteria derived from the evaluations can be used for the SOM-WSI design in the next step.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault-tolerant cube-connected cycles capable of quick broadcasting","authors":"N. Tsuda","doi":"10.1109/ICISS.1996.552443","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552443","url":null,"abstract":"The construction of fault-tolerant processor arrays with interconnections of cube-connected cycles (CCCs) by using an advanced spare-connection scheme for k-out-of-n redundancies called \"generalized additional bypass linking\" is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The spare connections are designed as a node-coloring problem of a CCC graph with a minimum distance of 3: the chromatic numbers corresponding to the number of spare PE connections were evaluated theoretically. The proposed scheme can be used for constructing various k-out-of-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control. In particular, it allows construction of optimal r-fault-tolerant configurations that provide r spare PEs and r extra connections per PE for CCCs with 4*x PEs (x: integer) in each cycle.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124381129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A defect-tolerant word-oriented static RAM with built-in self-test and self-reconfiguration","authors":"P. Nordholz, J. Otterstedt, D. Niggemeyer","doi":"10.1109/ICISS.1996.552419","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552419","url":null,"abstract":"In this paper, an efficient method for self-test and self-reconfiguration for a word-oriented single-port static RAM is presented. First, a suitable test algorithm is chosen and implemented as a built-in self-test (BIST) with low area overhead. Further, a circuit is developed which analyses the BIST signature and, in the event of a detected error, automatically reconfigures the memory utilising redundant cells in form of rows and blocks replacing the defective ones. In the presented approach a two-level redundancy has been implemented. Therefore, the RAM is split up into several blocks. On the lower level, each block is equipped with additional memory cells in the form of spare rows. On the higher level, additional redundant blocks are provided to mask larger defects. This hierarchical redundancy strategy leads to a considerably higher yield with comparatively low area overhead. To minimize the overhead, one has to consider the block size or the number of blocks, in which the RAM is split up, as the overhead strongly depends on it. An integrated chip has been manufactured and the functionality of the self-test and self-reconfiguration concept could be proved.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effects of scanning and biasing circuit restructuring on the response of a large area magnetic field sensor array","authors":"Y. Audet, G. Chapman","doi":"10.1109/ICISS.1996.552412","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552412","url":null,"abstract":"A large area magnetic field sensor array has been designed and fabricated with built-in redundancy using the laser-link technology as a restructuring tool. The sensor system response is measured and calibrated with a general regression analysis method. An algorithm to evaluate the effects of the restructuring schemes of the biasing and scanning circuits on the response is presented. From these first results, influence of the biasing circuit on the sensitivity of the sensor system is established and modification in the post-processing technique to reduce chip damage are required.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121275105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Hartenstein, J. Becker, M. Herz, U. Nageldinger
{"title":"A general approach in system design integrating reconfigurable accelerators","authors":"R. Hartenstein, J. Becker, M. Herz, U. Nageldinger","doi":"10.1109/ICISS.1996.552407","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552407","url":null,"abstract":"This paper introduces a fundamentally new machine paradigm, which takes into account that hardware has become soft. Along with a compilation technique, this paper introduces its implementation and application by illustrating the rDPA (reconfigurable data path array), an integrated circuit having been designed at Kaiserslautern and submitted for fabrication. This is the first implementation of a field-programmable data path array (FPDPA), which uses configurable ALU blocks (CABs) instead of CLBs (configurable logic blocks). This novel platform, provides highly efficient means of instruction level parallelism: for many applications by orders of magnitude more efficient than the traditional parallelism used in all scenes of high performance computing.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133922414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D. S. Wills, S. Yalamanchili
{"title":"Early analysis of cost/performance trade-offs in MCM systems","authors":"V. Garg, D. Schimmel, D. Stogner, C. Ulmer, D. S. Wills, S. Yalamanchili","doi":"10.1109/ICISS.1996.552430","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552430","url":null,"abstract":"This paper explores early analysis of the complex relationships between system architectures and the active and packaging materials from which they are implemented. The goals of this analysis are to enable the designer to specify cost effective technologies for a particular system and to uncover resources which may be exploited to increase performance of such a system, early in the design process. We describe a prototype tool called IMPACT which predicts cost, performance, power, and reliability, and demonstrate its use on several problems.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Moons, M. De Langhe, L. Kiss, E. Op de Beeck, J. Sevenhans
{"title":"An analog telephone subscriber chipset integrating 16 lines with fully programmable central office impedance","authors":"E. Moons, M. De Langhe, L. Kiss, E. Op de Beeck, J. Sevenhans","doi":"10.1109/ICISS.1996.552425","DOIUrl":"https://doi.org/10.1109/ICISS.1996.552425","url":null,"abstract":"This paper describes the chipset (3 ASIC's) for an analog telephone subscriber line circuit: a 16 channel digital circuit performing speech band filtering, echo cancellation, A-law//spl mu/-law coding and controlling interface, an 8 channel analog/digital circuit performing the A/D and D/A conversion with analog filtering, and an analog high voltage BICMOS circuit covering the SLIC (Subscriber Line Interface Circuit) function with special attention for the integration of software programmable synthesized AC and DC impedances.","PeriodicalId":131620,"journal":{"name":"1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon","volume":"16 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120856094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}