Reduced complexity SIMD-class architectures

Abstract

System engineering applied in leading microelectronic technologies requires novel computing architectures. These architectural counterparts of emerging technologies are expected to be dramatically different from existing architectural paradigms. To address this need, we are introducing a class of architectures which maintain computing robustness and reduced complexity in the interconnect domain, and still substantially differ from well established systolic systems. A class representative, a DRAM based system, is described in detail, with a permutation generation as an example of application.