Array-based testing of FPGAs: architecture and complexity

Abstract

This paper analyzes the architectural and complexity features of the array-based testing technique for field programmable gate arrays (FPGAs). The analysis is pursued using a hybrid (functional/stuck-at) single fault model by considering both the architecture of the configurable logic block (CLB) as well as the whole FPGA. Its evaluation using three commercially available FPGA families by Xilinx is presented in detail; emphasis is given to the different array configurations which permit the observability/controllability requirements of the testing process to satisfy the input/output restrictions (given by the I/O pins) of the FPGA, while still reducing the number of required programming phases.