Testability analysis of pipelined data paths

The problem of testability analysis for data-processing oriented architectures is considered. In particular, this paper concentrates on the analysis of pipelined architectures containing registers which act as data storage. A testability analyzer is proposed which accepts an RTL description of a complex device and automatically identifies the possible critical areas, i.e. those areas which seem the more difficult to test. The proposed testability analysis allows significant reduction of the area overhead and the test cost required for such kind of devices.