1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)最新文献

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A successful application of WLR fast test on Al via process optimisation 通过过程优化,成功地将WLR快速测试应用于人工智能
X. Liu, K. Lo, Q. Guo, J. Cai
{"title":"A successful application of WLR fast test on Al via process optimisation","authors":"X. Liu, K. Lo, Q. Guo, J. Cai","doi":"10.1109/IRWS.1999.830562","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830562","url":null,"abstract":"In this paper, a successful application of WLR fast electromigration (EM) test on Al via process optimization is presented. The impact of spin-on-glass (SOG) and pre sputter etch (PSE) on via performance is characterised by using standard wafer-level electromigration accelerated test (SWEAT). By eliminating the potential of SOG outgassing at the via and optimizing per sputter etch oxide loss (PSEOL), the optimization of the via process has been achieved with a 10% reduction in via resistance and a 6.5% improvement in yield.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130222182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
(Ultra)thin oxide breakdown(s), an overview (超)薄氧化物分解(s),概述
E. Vincent
{"title":"(Ultra)thin oxide breakdown(s), an overview","authors":"E. Vincent","doi":"10.1109/IRWS.1999.830587","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830587","url":null,"abstract":"This paper briefly reviews the main degradation mechanisms which occur in thin oxides during Fowler-Nordheim electron injection in order to better highlight the evolutions of the oxide failure modes when scaling down the oxide thickness. In particular, the impact of the oxide thickness scaling down on the breakdown phenomena is analyzed. Moreover, the quasi-breakdown phenomenon, a new failure mode observed in ultrathin oxides, is described and a methodology to rigorously address the ultrathin oxide reliability is given.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131177142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Reliability test results for W FIB interconnect structures wfib互连结构可靠性试验结果
M. Zaragoza, Jingwei Zhang, M. Abramo
{"title":"Reliability test results for W FIB interconnect structures","authors":"M. Zaragoza, Jingwei Zhang, M. Abramo","doi":"10.1109/IRWS.1999.830553","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830553","url":null,"abstract":"The reliability of W-based FIB modifications is assessed through the stress testing of FIB test structures. Three structure types were created that examined the integrity of vias, lines, and FIB-deposited insulator material. Structures were stressed at 125/spl deg/C with no current for 3900 hours and 170/spl deg/C with current for 2700 hours. Structures were also temperature cycled for 2000 cycles. Electrical resistance remained stable throughout all stress conditions and there was no evidence of degradation to the FIB-deposited W or SiO/sub 2/ films or to the Al lines. The only failure observed was with the insulator material due to misalignment of the structure.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures 信号裕度测试,以确定在低温下与DRAM可靠性和功能相关的工艺灵敏度
E. Nelson, Y. Li, D. Poindexter, M. Ruprecht, E. Lim, Y. Matsubara, H. Sawazaki, Q. Ye, M. Iwatake, W. Tonti
{"title":"Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures","authors":"E. Nelson, Y. Li, D. Poindexter, M. Ruprecht, E. Lim, Y. Matsubara, H. Sawazaki, Q. Ye, M. Iwatake, W. Tonti","doi":"10.1109/IRWS.1999.830551","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830551","url":null,"abstract":"With high aspect ratio, tight spacing, small line widths, and low supply voltages associated with the scaling of the DRAM cell, signal for the sense amplifier becomes weaker for each new DRAM generation. We have developed a signal margin testing methodology capable of identifying process sensitivities relevant to DRAM functionality and reliability at low temperatures. This paper describes the test methodology and discusses the benefits derived from applying this method to 256M DRAM product development.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124233211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Detecting breakdown in ultra-thin dielectrics using a fast voltage ramp 使用快速电压坡道检测超薄电介质的击穿
E. Snyder, J. Suehle
{"title":"Detecting breakdown in ultra-thin dielectrics using a fast voltage ramp","authors":"E. Snyder, J. Suehle","doi":"10.1109/IRWS.1999.830571","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830571","url":null,"abstract":"We propose a voltage ramp technique which detects ultra-thin oxide breakdown when other techniques (such as noise) fail. This technique provides a straightforward method of extending conventional ramp breakdown techniques to ultra-thin dielectrics (<3.5 nm). This technique monitors the use-condition current (or current below stress current) after each stress-step in the ramp. We apply this method to a wide range of oxide areas and gate oxide thicknesses. We show for the first time that the post-stress leakage current is independent of oxide area over 7 orders of magnitude and for 5 oxide thickness from 20 nm to 2.3 nm. In addition, we show that the voltage ramp Weibull distribution statistics scale with area and are consistent with constant voltage stress tests on 2 nm gate oxides. We model the post-breakdown I-V characteristics and show a space-charge limited behavior. This observation is used to explain why a modified voltage ramp technique is needed for ultra-thin oxides and defect-detecting large area structures. Finally, we demonstrate that new noise techniques may be necessary to detect breakdown during constant voltage stress in ultra-thin gate oxides.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114127106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Simulation of hot-carrier degradation using self-consistent solution of semiconductor energy-balance equations and oxide carrier transport equations 利用半导体能量平衡方程和氧化物载流子输运方程的自一致解模拟热载流子退化
S. Mukundan, M. Pagey, peixiong zhao, K. Galloway
{"title":"Simulation of hot-carrier degradation using self-consistent solution of semiconductor energy-balance equations and oxide carrier transport equations","authors":"S. Mukundan, M. Pagey, peixiong zhao, K. Galloway","doi":"10.1109/IRWS.1999.830565","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830565","url":null,"abstract":"The Si-SiO/sub 2/ interface has been modelled as an abrupt heterojunction to simulate hot-carrier injection and transport in oxides of n- and p-channel MOSFETs. Energy balance equations in silicon and continuity equations in the oxide and silicon regions are solved consistently with trapping-rate equations in the oxide to simulate hot-carrier induced carrier trapping and interface trap generation.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116033392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hot-carrier damage in AC-stressed deep submicrometer CMOS technologies 交流应力深亚微米CMOS技术中的热载流子损伤
A. Bravaix, D. Goguenheim, N. Revil, Emmanuel Vincent
{"title":"Hot-carrier damage in AC-stressed deep submicrometer CMOS technologies","authors":"A. Bravaix, D. Goguenheim, N. Revil, Emmanuel Vincent","doi":"10.1109/IRWS.1999.830559","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830559","url":null,"abstract":"We have investigated the degradation behavior of single transistors using DC and AC alternating stress conditions as the interface trap generation and the charge trapping/detrapping phenomena become a competitive interaction during AC cycles in 0.25 /spl mu/m CMOS technologies with 5 nm thick gate-oxide. In this way, we determine to what extent the effects and mechanisms are affecting the resultant degradation behavior between N- and P-MOSFETs in order to explain the degradation observed in actual circuits. The effect of temperature is further investigated between -40/spl deg/C and 125/spl deg/C as Negative Bias Temperature Instability (NBTI), thermal emission, field-enhanced charge detrapping may contribute to the transistor degradation and modify the circuit degradation. We verify the usefulness of the experimental procedure and model based on duty cycle calculations for ring oscillators.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129104339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Impact of Si/N ratios in a pre-metal Si/sub x/N/sub y/:H/sub z/ dielectric film on NMOS channel hot carrier reliability 预金属Si/sub x/N/sub y/:H/sub z/介质膜中Si/N比对NMOS通道热载流子可靠性的影响
J. Masin, R. Mena, M. Brugler, B. Rajagopalan
{"title":"Impact of Si/N ratios in a pre-metal Si/sub x/N/sub y/:H/sub z/ dielectric film on NMOS channel hot carrier reliability","authors":"J. Masin, R. Mena, M. Brugler, B. Rajagopalan","doi":"10.1109/IRWS.1999.830585","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830585","url":null,"abstract":"The effect of silicon to nitrogen ratios in a pre-metal silicon nitride dielectric film on NMOSFET channel hot carrier (CHC) reliability is studied. Si/sub x/N/sub y/:H/sub z/ films are deposited with Si/N ratios of 0.9 and 0.7. Wafer level hot carrier data shows transistors built with a silicon rich liner have a 4.5/spl times/ higher CHC lifetime. Charge pump measurements are carried out and indicate an increase in D/sub it/ for a wafer with a nitrogen rich liner. It is shown that the nitrogen rich film releases less hydrogen during subsequent processing resulting in less hydrogen passivation of the Si/SiO/sub 2/ surface and increased D/sub it/. The observed lifetime reduction is a result of the increase in D/sub it/. Finally, it is demonstrated that despite an end-of-line anneal in a hydrogen ambient, hydrogen exposure early in the fabrication process can play an important role in Si/SiO/sub 2/ surface passivation, affecting CHC reliability.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"11632 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131542124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Conduction mechanisms in Cu/low-k interconnect 铜/低钾互连中的传导机制
G. Bersuker, V. Blaschke, S. Choi, D. Wick
{"title":"Conduction mechanisms in Cu/low-k interconnect","authors":"G. Bersuker, V. Blaschke, S. Choi, D. Wick","doi":"10.1109/IRWS.1999.830561","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830561","url":null,"abstract":"Electrical characterization of Cu/low-k structures was performed to address intrinsic material properties. It was shown that ionic conduction due to contamination inherent to the dielectric was the leading cause of an intrinsic intra-metal line leakage current at low temperatures, while at elevated temperatures a contribution from electron current was detected. Dielectric and barrier layer parameters that control the conduction process were evaluated.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131577022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dependence of HCI mechanism on temperature for 0.18 /spl mu/m technology and beyond 0.18 /spl mu/m及以上工艺的HCI机制对温度的依赖性
Weizhong Wang, J. Tao, P. Fang
{"title":"Dependence of HCI mechanism on temperature for 0.18 /spl mu/m technology and beyond","authors":"Weizhong Wang, J. Tao, P. Fang","doi":"10.1109/IRWS.1999.830560","DOIUrl":"https://doi.org/10.1109/IRWS.1999.830560","url":null,"abstract":"We have studied the temperature impact on the substrate current. For both NMOS and PMOS, the peak substrate current increases with the temperature at low drain bias. An analytical model was proposed to explain this result. More important, the HCI degradation under different temperatures was studied. The NMOS HCI degradation mechanism still follows the lucky electron model, while PMOS HCI degradation is faster at higher temperature for the same peak substrate current. The RO AC HCI test shows little change due to temperature impact. This is because NMOS degrades much faster than PMOS.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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