Dependence of HCI mechanism on temperature for 0.18 /spl mu/m technology and beyond

We have studied the temperature impact on the substrate current. For both NMOS and PMOS, the peak substrate current increases with the temperature at low drain bias. An analytical model was proposed to explain this result. More important, the HCI degradation under different temperatures was studied. The NMOS HCI degradation mechanism still follows the lucky electron model, while PMOS HCI degradation is faster at higher temperature for the same peak substrate current. The RO AC HCI test shows little change due to temperature impact. This is because NMOS degrades much faster than PMOS.