Hot-carrier damage in AC-stressed deep submicrometer CMOS technologies

Abstract

We have investigated the degradation behavior of single transistors using DC and AC alternating stress conditions as the interface trap generation and the charge trapping/detrapping phenomena become a competitive interaction during AC cycles in 0.25 /spl mu/m CMOS technologies with 5 nm thick gate-oxide. In this way, we determine to what extent the effects and mechanisms are affecting the resultant degradation behavior between N- and P-MOSFETs in order to explain the degradation observed in actual circuits. The effect of temperature is further investigated between -40/spl deg/C and 125/spl deg/C as Negative Bias Temperature Instability (NBTI), thermal emission, field-enhanced charge detrapping may contribute to the transistor degradation and modify the circuit degradation. We verify the usefulness of the experimental procedure and model based on duty cycle calculations for ring oscillators.