E. Nelson, Y. Li, D. Poindexter, M. Ruprecht, E. Lim, Y. Matsubara, H. Sawazaki, Q. Ye, M. Iwatake, W. Tonti
{"title":"Signal margin test to identify process sensitivities relevant to DRAM reliability and functionality at low temperatures","authors":"E. Nelson, Y. Li, D. Poindexter, M. Ruprecht, E. Lim, Y. Matsubara, H. Sawazaki, Q. Ye, M. Iwatake, W. Tonti","doi":"10.1109/IRWS.1999.830551","DOIUrl":null,"url":null,"abstract":"With high aspect ratio, tight spacing, small line widths, and low supply voltages associated with the scaling of the DRAM cell, signal for the sense amplifier becomes weaker for each new DRAM generation. We have developed a signal margin testing methodology capable of identifying process sensitivities relevant to DRAM functionality and reliability at low temperatures. This paper describes the test methodology and discusses the benefits derived from applying this method to 256M DRAM product development.","PeriodicalId":131342,"journal":{"name":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE International Integrated Reliability Workshop Final Report (Cat. No. 99TH8460)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRWS.1999.830551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
With high aspect ratio, tight spacing, small line widths, and low supply voltages associated with the scaling of the DRAM cell, signal for the sense amplifier becomes weaker for each new DRAM generation. We have developed a signal margin testing methodology capable of identifying process sensitivities relevant to DRAM functionality and reliability at low temperatures. This paper describes the test methodology and discusses the benefits derived from applying this method to 256M DRAM product development.