IEEE Transactions on Electron Devices最新文献

{"title":"Hot Carrier Degradation-Induced Variability in Different Lightly Doped Drain Processes: From Transistors to SRAM Cells","authors":"Qiao Teng;Yongyu Wu;Kai Xu;Dawei Gao","doi":"10.1109/TED.2024.3462380","DOIUrl":"https://doi.org/10.1109/TED.2024.3462380","url":null,"abstract":"In this work, the impact of lightly doped drain (LDD) implantation doses on hot carrier degradation (HCD) variability behaviors has been studied for transistors and static random access memory (SRAM) cells. It is found that threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {T}}$ </tex-math></inline-formula>\u0000) variability is enhanced, while the saturation current (\u0000<inline-formula> <tex-math>${I}_{text {D}}$ </tex-math></inline-formula>\u0000) variability is suppressed for n-type MOSFETs (n-MOSFETs) and p-type MOSFETs (p-MOSFETs) during HCD. Nonuniform trap generation and the current self-convergence mechanism are used to explain the reason for variability, respectively. Devices fabricated at higher LDD doses have lower variability, which is attributed to improved quasi-ballistic transport characteristics. Furthermore, the impacts of HCD on the static noise margin (SNM) variability of SRAM cells in the hold and read state are also inhibited with the increased LDD doses due to the descending variability in individual transistors. Therefore, LDD process optimization is beneficial for transistors and circuits against HCD variability without additional design margin.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6527-6533"},"PeriodicalIF":2.9,"publicationDate":"2024-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Threshold Voltage Stability in AlGaN/GaN MIS-HEMT Structure Under Cryogenic Environment","authors":"Yi-Ho Chen;Fu-Chuan Chu;M. Uma;Muhammad Aslam;Yao-Jen Lee;Yiming Li;Seiji Samukawa;Yeong-Her Wang","doi":"10.1109/TED.2024.3457581","DOIUrl":"https://doi.org/10.1109/TED.2024.3457581","url":null,"abstract":"The electrical behavior of AlGaN/GaN Schottky-gate high-electron mobility transistors (HEMTs) and metal-insulator–semiconductor HEMTs (MIS-HEMTs) at cryogenic temperatures ranging down to 10 K is investi- gated in this research. The well-known reliability issues in oxide transistors, such as current collapse and threshold voltage (\u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000) variations, emphasize the necessity of such studies. A more pronounced \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 variation in MIS-HEMTs compared to Schottky-gate HEMTs is observed, which is attributed to the presence of acceptor-like defect states within the oxide layer. The negative \u0000<inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula>\u0000 shift in MIS-HEMTs can be ascribed to the reduced thermionic emission of electrons. These findings are validated through bias temp- erature instability tests. These insights offer perspectives on the performance differences between the two transistor configurations in cryogenic environments.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6566-6572"},"PeriodicalIF":2.9,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of the Fabrication Process for Phototransistors With IGZO/TiOx Bilayer Thin Films to Improve Electrical and Photoresponse Characteristics","authors":"Jae-Yun Lee;Gergely Tarsoly;Sang-Bong Lee;Jin-Hee Lee;Sung-Jin Kim","doi":"10.1109/TED.2024.3462379","DOIUrl":"https://doi.org/10.1109/TED.2024.3462379","url":null,"abstract":"Metal oxides are among the most popular research targets in electronic materials for their high charge carrier mobility, transparency, and versatility. Recently, semiconductors based on multilayers of oxide thin films have attracted interest for applications, such as resistive memories or phototransistors. Here, a phototransistor was fabricated based on a bilayer of indium gallium zinc oxide (IGZO) and nonstochiometric, oxygen-deficient titanium oxide (TiOx) thin films formed via sputtering. The device fabrication was optimized by varying the temperature of the thermal annealing step to enhance the electrical performance and photoresponse characteristics. The IGZO/TiOx bilayer-based devices exhibited maximal performance when annealed at 350 °C with good mobility, low subthreshold swing, a turn-on voltage around 0 V, and high photoresponse through a wide range of gate bias. The dynamic photoresponse was evaluated under discrete light pulses. The device characteristics were measured after storage in an exicator for more than five months, and reasonable stability in photoresponse was observed.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6738-6742"},"PeriodicalIF":2.9,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Top SiO₂ Interlayer Thickness on Memory Window of Si Channel FeFET With TiN/SiO₂/Hf₀.₅Zr₀.₅O₂/SiOx/Si (MIFIS) Gate Structure","authors":"Tao Hu;Xianzhou Shao;Mingkai Bai;Xinpei Jia;Saifei Dai;Xiaoqing Sun;Runhao Han;Jia Yang;Xiaoyu Ke;Fengbin Tian;Shuai Yang;Junshuai Chai;Hao Xu;Xiaolei Wang;Wenwu Wang;Tianchun Ye","doi":"10.1109/TED.2024.3459873","DOIUrl":"https://doi.org/10.1109/TED.2024.3459873","url":null,"abstract":"We study the impact of top SiO2 interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistor (FeFET) with TiN/SiO2/ Hf0.5Zr0.5O2/SiOx/Si (MIFIS) gate structure. We find that the MW increases with the increasing thickness of the top SiO2 interlayer, and such an increase exhibits a two-stage linear dependence. The physical origin is the presence of the different interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface. Moreover, we investigate the dependence of endurance characteristics on initial MW. We find that the endurance characteristic degrades with increasing the initial MW. Meanwhile, we study the impact of the top SiO2 interlayer thickness on the retention characteristics of the MIFIS structure. The results of retention characteristics show that the MIFIS structure with thicker top SiO2 has poorer retention characteristics. This is attributed to the de-trapping of interfacial charges trapped at the top SiO2/Hf0.5Zr0.5O2 interface and the depolarization field of the ferroelectric. By inserting a 3.4 nm SiO2 dielectric interlayer between the gate metal TiN and the ferroelectric Hf0.5Zr0.5O2, we achieve a MW of 6.3 V and retention over 10 years. Our work is helpful in the device design of FeFET.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6698-6705"},"PeriodicalIF":2.9,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-Driven β-Ga2O3 Solar-Blind Deep-Ultraviolet Photodetectors With Asymmetric MXene Electrodes","authors":"Chao Xie;Xisheng Cui;Shijie Xu;Yu Cheng;Liangpan Yang;Wenhua Yang;Zhixiang Huang","doi":"10.1109/TED.2024.3454590","DOIUrl":"https://doi.org/10.1109/TED.2024.3454590","url":null,"abstract":"Here, a \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 solar-blind deep-ultraviolet (DUV) photodetector operating in self-driven mode is designed. MXene films with diverse work functions enabled by different doping are drop-coated at opposite ends of a \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3 microflake to serve as asymmetric electrodes. The different work functions bring about a strong built-in electric field, rendering a pronounced photovoltaic (PV) effect. As a consequence, the light detector reaches a large Ilight/\u0000<inline-formula> <tex-math>${I} _{text {dark}}$ </tex-math></inline-formula>\u0000 ratio of \u0000<inline-formula> <tex-math>$10^{{3}}$ </tex-math></inline-formula>\u0000, a low dark current of sub-pA, a decent responsivity of 9.81 mA/W, a respectable specific detectivity of \u0000<inline-formula> <tex-math>$10^{{11}}$ </tex-math></inline-formula>\u0000 Jones, and a fast response speed of 10.2/17.7 ms, along with good operational stability, at zero bias, upon 254 nm light. The DUV/ultraviolet rejection ratio can attain \u0000<inline-formula> <tex-math>$10^{{3}}$ </tex-math></inline-formula>\u0000. A flexible device also holds robust durability at various bending states. The study provides a viable route for constructing efficient DUV light detectors and is also helpful for developing MXene-based optoelectronic devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6804-6808"},"PeriodicalIF":2.9,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced Endurance and Stability of FDSOI Ferroelectric FETs at Cryogenic Temperatures for Advanced Memory Applications","authors":"Miaomiao Zhang;Haoji Qian;Jiacheng Xu;Minglei Ma;Rongzong Shen;Gaobo Lin;Jiani Gu;Yan Liu;Chengji Jin;Jiajia Chen;Genquan Han","doi":"10.1109/TED.2024.3456763","DOIUrl":"https://doi.org/10.1109/TED.2024.3456763","url":null,"abstract":"In this work, we have systematically characterized the ferroelectric (FE) and memory properties in the fully depleted silicon-on-insulator (FDSOI) FE field-effect transistor (FeFET) across a temperature range of 300–5 K. At a deep cryogenic temperature of 5 K, the endurance of multipolarization states in Hf0.5Zr0.5O2 (HZO) gate-stack exhibits a significant improvement compared to that at 300 K. Especially for states of partial switching polarization under low voltage, it is expected to achieve endurance immunity. This can be attributed to that oxygen vacancies are more difficult to redistribute at cryogenic temperature. Furthermore, compared to 300 K, the performance of multilevel cell FDSOI FeFET at 5 K demonstrates higher stability, providing a promising solution for cryogenic memory and computing systems with low power and high stability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6680-6685"},"PeriodicalIF":2.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Defect-Engineered Resistive Switching in van der Waal Metals","authors":"B. Manoj Kumar;C. Malavika;E. S. Kannan","doi":"10.1109/TED.2024.3457730","DOIUrl":"https://doi.org/10.1109/TED.2024.3457730","url":null,"abstract":"In this work, we demonstrated bipolar resistive switching (RS) in van der Waals metals [tantalum di-sulfide (2H-TaS2), tantalum di-selenide (2H-TaSe2)], and their heterostructures (2H-TaS2/2H-TaSe2) by engineering defects through joule heating mechanism. Localized heating is achieved by injecting current to the van der Waals metals and the induced defects were found to be mostly chalcogenide vacancies. The vacancies act as dynamic charge-trapping and de-trapping sites within the material structure, thereby inducing RS in the device. The SET/RESET process is controlled by changing the direction of the current flow, a behavior that is very similar to that of a memristor. But unlike a memristor, the reported device has a completely different architecture with no oxide or semiconducting active layer. Temperature-dependent studies revealed that the carrier transport is dominated by space-charge limited conduction and sharp switching occurs due to the voltage-driven modulation of potential barrier heights at the region containing the defects. The study offers a simple alternative to conventional two-terminal resistive switches and the potential of van der Waals metals for the advancement of memristive devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"7144-7148"},"PeriodicalIF":2.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142517876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Schottky Diodes Based on Amorphous Ga2O3 Thin Films by UV-Ozone Treatment","authors":"Limeng Chen;Guangtan Miao;Hongfu Xie;Wenlan Xiao;Guoxia Liu;Fukai Shan","doi":"10.1109/TED.2024.3456772","DOIUrl":"https://doi.org/10.1109/TED.2024.3456772","url":null,"abstract":"In this report, amorphous Ga2O3 thin film was prepared by magnetron sputtering, and the Schottky barrier diodes (SBDs) based on amorphous Ga2O3 thin films were fabricated. The electrical performances of the SBDs based on amorphous Ga2O3 thin films with different UV-ozone (UVO) treatment conditions were systematically studied. It is found that the oxygen vacancies at the interface of the SBDs can be suppressed by the UVO treatment. The UVO-optimized SBDs exhibit superior electrical performance, including the near-unity ideality factor of 1.12, a Schottky barrier height of 1.05 eV, and a high rectification ratio of \u0000<inline-formula> <tex-math>$7.08times 10^{{8}}$ </tex-math></inline-formula>\u0000. This method confirms the great potential for SBDs based on amorphous oxide semiconductors (AOSs) in the future.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6910-6914"},"PeriodicalIF":2.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Properties of Multi-Junction Cascade Vertical Cavity Surface Emitting Lasers","authors":"Xiaoli Zhou;Yinuo Wang;Meng Xun;Guanzhong Pan;Yun Sun;Runze Zhang;Weichao Wu;Song Wu;Yongming Fei;Xiaowei Jiang;Dexin Wu","doi":"10.1109/TED.2024.3456769","DOIUrl":"https://doi.org/10.1109/TED.2024.3456769","url":null,"abstract":"Multi-junction cascade vertical cavity surface emitting lasers (VCSELs) exhibit a noteworthy thermal issue because of their multiple active regions. We have designed and fabricated two six-junction cascade VCSELs with different oxide layers. The light-current–voltage (L–I–V) and divergence angle characteristics, as well as their thermal properties at various ambient temperatures, were analyzed to investigate the thermal problems. Based on the relationship between the emission spectra and power dissipation, we were able to obtain the corresponding thermal resistance values and active region temperatures of different structures afterward. It turned out that the multi-junction cascade VCSELs with multioxide layers have evident advantages of slope efficiency (SE) and optical output power over those with a single-oxide layer due to excellent current and optical confinement. However, owing to the low thermal conductivity of the oxide layers, it is difficult for the heat generated in the active regions to transfer to the surrounding area, resulting in an increase in the thermal resistance of multioxide VCSELs. Meanwhile, the divergence angle of multioxide VCSELs becomes larger because of the strong optical confinement. For better insight, a heat diffusion model of these two devices was established, and the temperature distribution was analyzed. Both the simulation and experimental results agreed fairly well.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6831-6837"},"PeriodicalIF":2.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric–Insulator-Si (MFIS) FeFET","authors":"Giuk Kim;Hyojun Choi;Sangho Lee;Hunbeom Shin;Sangmok Lee;Yunseok Nam;Hyunjun Kang;Seokjoong Shin;Hoon Kim;Youngjin Lim;Kang Kim;Il-Kwon Oh;Sang-Hee Ko Park;Jinho Ahn;Sanghun Jeon","doi":"10.1109/TED.2024.3442163","DOIUrl":"https://doi.org/10.1109/TED.2024.3442163","url":null,"abstract":"In this study, we investigated the impact of unstable and stable interface trap charges (\u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}text {)}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 on \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 switching in metal-ferroelectric–insulator-Si (MFIS) ferroelectric field-effect transistors (FeFETs), which vary with the thickness of the insulator. We also examine how these variations ultimately affect the various performance metrics of MFIS FeFETs. To achieve this, we varied the thickness of the insulator (\u0000&lt;inline-formula&gt; &lt;tex-math&gt;${t}_{text {IL}}text {)}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 in MFIS FeFETs to 1.5, 2.0, and 2.5 nm, thereby controlling the amount of \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 injected from the channel into the ferroelectric (FE)/insulator interface. As \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${t}_{text {IL}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 decreases, the amount of \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 increases, which amplifies the electric field across the FE layer. As a result, \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 switching enhances, and consequently, the MW characteristics of MFIS FeFETs improve. Furthermore, to analyze this in detail, we employed \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000–\u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 measurements on MFIS FeFETs to simultaneously extract unstable and stable \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 as well as \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 and MW. The results show that as \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${t}_{text {IL}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 increases to 1.5, 2.0, and 2.5 nm, \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 during program/erase (PGM/ERS) operations decreases to 100%, 61%, and 54%, respectively. This leads to a corresponding decrease in \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 to 100%, 59%, and 52%. Additionally, after sufficient delay following the PGM/ERS operations, we observe that the proportion stable \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 compared to \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 is 91%, regardless to \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${t}_{text {IL}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 and the remaining 9% of \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${P}_{text {S}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 contributes to the MW property. Consequently, as \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${t}_{text {IL}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;\u0000 increases to 1.5, 2.0, and 2.5 nm, the net charge decreases to 100%, 61%, and 54%, resulting in MW values of 1.85, 1.05, and 0.85 V, respectively. Finally, we analyzed the impact of \u0000&lt;inline-formula&gt; &lt;tex-math&gt;${Q}_{text {it}}","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"71 11","pages":"6627-6632"},"PeriodicalIF":2.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142518242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}