IEEE Transactions on Electron Devices最新文献_第8页

A Multiphysics Simulation Framework for Electromigration Risk Assessment in Modern Interconnects 现代互连中电迁移风险评估的多物理场仿真框架

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-22 DOI: 10.1109/TED.2025.3588467

Binyu Yin;Linlin Cai;Haoyu Zhang;Wangyong Chen

引用次数: 0

Toward Generation of Megawatt Subnanosecond Microwave Pulses With High Repetition Rate 高重复频率的兆瓦亚纳秒微波脉冲的产生

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-22 DOI: 10.1109/TED.2025.3579437

Zhiyuan Zhang;Weijie Wang;Ruoyang Pan;Yelei Yao;Wei Jiang;Zewei Wu;Youlei Pu;Jianxun Wang;Yong Luo;Guo Liu

引用次数: 0

Indexing Current–Voltage Characteristics Using a Hash Function 使用哈希函数索引电流-电压特性

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-21 DOI: 10.1109/TED.2025.3588498

T. Tanamoto;S. Furukawa;R. Kitahara;T. Mizutani;K. Ono;T. Hiramoto

引用次数: 0

Meta-Optimized LDMOS Process–Device Co-Optimization: Extrapolation-Enhanced Modeling With Wafer-Level Validation 元优化LDMOS工艺-器件协同优化：外推增强建模与晶圆级验证

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-18 DOI: 10.1109/TED.2025.3588137

Yuxuan Zhu;Hongyu Tang;Yan Pan;Ping Ouyang;Yitao Ma;Kai Xu

{"title":"Meta-Optimized LDMOS Process–Device Co-Optimization: Extrapolation-Enhanced Modeling With Wafer-Level Validation","authors":"Yuxuan Zhu;Hongyu Tang;Yan Pan;Ping Ouyang;Yitao Ma;Kai Xu","doi":"10.1109/TED.2025.3588137","DOIUrl":"https://doi.org/10.1109/TED.2025.3588137","url":null,"abstract":"Accurate and efficient modeling of lateral double-diffused MOS (LDMOS) devices is critical for process optimization and reliability analysis, especially under limited simulation budgets. However, data-driven modeling for semiconductor devices faces three key challenges: limited training data due to the high cost of technology computer-aided design (TCAD) and silicon measurements; poor generalization to extrapolated or extreme configurations; and a gap between simulation and measured data, which undermines predictive reliability in practical use cases. To address these issues, this work presents a model-agnostic meta-learning (MAML) framework that improves the prediction accuracy and adaptability of deep neural networks and convolutional neural networks (CNNs) for TCAD-based process–device modeling. To further evaluate generalization to extrapolated scenarios, we introduce an additional dataset of samples whose input parameters lie within the design space but whose electrical outputs are near or beyond the original training range. This setup mimics real-world edge cases where accurate prediction is essential for safe operating area (SOA) design. Subsequently, k-means clustering is used to define distinct tasks, enabling task-specific fine-tuning. MAML-based models show significant performance improvements under this configuration, approaching in-distribution accuracy. Moreover, wafer-level experiments further validate the model’s guidance, confirming improvements in breakdown voltage without compromising on-resistance. Taken together, these results demonstrate that the proposed MAML framework effectively enhances model generalization and sample efficiency in semiconductor device modeling, supporting scalable and robust prediction under data-limited and distribution-shifted conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5089-5096"},"PeriodicalIF":3.2,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Study of Parasitic Capacitance in CFETs: An Analytical Perspective cfet中寄生电容的综合研究：一个分析的视角

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-18 DOI: 10.1109/TED.2025.3585907

Aishwarya Singh;Jaisingh Pal;Om Maheshwari;Nihar R. Mohapatra

引用次数: 0

Effects of Unipolar and Bipolar Pulses on Leakage and Breakdown in HZO-Based FeFETs: A Path to Improved Endurance 单极和双极脉冲对hzo基效应场效应管泄漏和击穿的影响：提高耐用性的途径

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-17 DOI: 10.1109/TED.2025.3587635

Mingkai Bai;Xiaoqing Sun;Tao Hu;Yajing Ding;Xinpei Jia;Runhao Han;Xiaoyu Ke;Junshuai Chai;Kai Han;Hao Xu;Xiaolei Wang;Wenwu Wang;Tianchun Ye

{"title":"Effects of Unipolar and Bipolar Pulses on Leakage and Breakdown in HZO-Based FeFETs: A Path to Improved Endurance","authors":"Mingkai Bai;Xiaoqing Sun;Tao Hu;Yajing Ding;Xinpei Jia;Runhao Han;Xiaoyu Ke;Junshuai Chai;Kai Han;Hao Xu;Xiaolei Wang;Wenwu Wang;Tianchun Ye","doi":"10.1109/TED.2025.3587635","DOIUrl":"https://doi.org/10.1109/TED.2025.3587635","url":null,"abstract":"Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistors (FeFETs) show great promise for nonvolatile memory (NVM) applications, but their endurance faces major challenges, with breakdown being a key limiting factor. In this study, we investigated the leakage behavior and breakdown mechanisms of FeFETs under varying unipolar positive, unipolar negative, and bipolar pulse amplitudes using carrier separation method. We identified distinct breakdown mechanisms for each pulse type: 1) unipolar positive pulses drive defects to form a breakdown path (BD path) rather than the generation of new defects, in addition, the breakdown characteristics are different depending on the location of the BD path; 2) a unipolar negative pulse suppresses defects movement but generates new defects, and near the SiO2 interfacial layer (IL) traps positive charges, increasing the electric field at the HZO layer, which leads to the formation of the initial BD path in the HZO layer of the channel region; and 3) bipolar pulses accelerate defects generation, leading to the creation of multiple BD paths and breakdown. Based on these findings, we developed a recovery scheme using unipolar negative pulses, achieving over 100 successful recoveries. Controlling defects movement and generation is crucial for enhancing FeFETs endurance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4856-4864"},"PeriodicalIF":3.2,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling the Parasitic Capacitance of Nanosheet FETs With Backside Power Delivery Network 基于反向供电网络的纳米片场效应管寄生电容建模

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-17 DOI: 10.1109/TED.2025.3585478

Hengyi Liu;Sihao Chen;Baokang Peng;Heng Wu;Runsheng Wang;Lining Zhang

{"title":"Modeling the Parasitic Capacitance of Nanosheet FETs With Backside Power Delivery Network","authors":"Hengyi Liu;Sihao Chen;Baokang Peng;Heng Wu;Runsheng Wang;Lining Zhang","doi":"10.1109/TED.2025.3585478","DOIUrl":"https://doi.org/10.1109/TED.2025.3585478","url":null,"abstract":"This article presents a parasitic capacitance model for gate-all-around (GAA) nanosheet FETs (NsFETs) with backside power delivery network (BSPDN) including three types of techniques buried power rail (BPR), through Silicon Via in MOL (TSVM), and backside contact (BSC). Based on the electrical field analysis and elliptical integral method, the different parasitic capacitance components are extracted and accurately modeled. In addition, the variation in parasitic capacitance components with the structural parameters is also investigated for design optimization of NsFETs with BSPDN. The extra parasitic capacitance induced by the TSVM, BPR, and BSC accounts for about 19.4%, 14.1%, and 7.4% in the <inline-formula> <tex-math>${C}_{textit {gs}_{textit {para}}}$ </tex-math></inline-formula>(or <inline-formula> <tex-math>${C}_{textit {gd}_{textit {para}}}text {)}$ </tex-math></inline-formula>, respectively. Furthermore, the proposed models were integrated into a calibrated NsFET model, enabling an analysis of the parasitic capacitance induced by the BSPDN in the MEOL at the prelayout stage. The dynamic performance of the circuits, such as ring oscillators, is evaluated under various geometric parameters. This work provides insight into the design technology co-optimization of BSPDN technology in advanced nodes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4728-4734"},"PeriodicalIF":3.2,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of the Organic Buffer Layer on Charge Injection and Transport Characteristics in Organic Transistors With Different Channel Lengths 有机缓冲层对不同通道长度有机晶体管电荷注入和输运特性的影响

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-17 DOI: 10.1109/TED.2025.3586223

Walid Boukhili;Swelm Wageh;Quanhua Chen;Fathi Jomni;Xiang Wan;Zhihao Yu;Chee Leong Tan;Huabin Sun;Yong Xu;Dongyoon Khim

{"title":"Effect of the Organic Buffer Layer on Charge Injection and Transport Characteristics in Organic Transistors With Different Channel Lengths","authors":"Walid Boukhili;Swelm Wageh;Quanhua Chen;Fathi Jomni;Xiang Wan;Zhihao Yu;Chee Leong Tan;Huabin Sun;Yong Xu;Dongyoon Khim","doi":"10.1109/TED.2025.3586223","DOIUrl":"https://doi.org/10.1109/TED.2025.3586223","url":null,"abstract":"Extensive research on channel downscaling has led to notable advancements in semiconductor technology. Studying the size reduction of organic transistors remains an important task that necessitates a comprehensive understanding, especially for the short-channel effect. In this work, we investigated the impacts of the insertion of the organic buffer layer and channel length scaling on contact resistance, charge transport, and, consequently, the device performance. Incorporation of an organic buffer layer between the source/drain (S/D) electrodes and the organic semiconductor (OSC) leads to a substantially decreased contact resistance, closely correlated with improved drain-induced barrier lowering (DIBL) and interface trap density. This behavior is especially noticeable in devices with shorter channel lengths, where the contacts play a critical role in the whole charge transport. Our results provide insights into the development of upcoming electronic components, specifically in the field of organic field-effect transistor (OFET) device physics, with short channel lengths.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5123-5129"},"PeriodicalIF":3.2,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comparison of 14-MeV Neutron-Induced Damage in Si and SiC Power MOSFETs 硅和SiC功率mosfet中14-MeV中子致损伤的比较

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-17 DOI: 10.1109/TED.2025.3588129

Chao Peng;Hong Zhang;Zhangang Zhang;Teng Ma;Zhizhe Wang;Zhifeng Lei

{"title":"Comparison of 14-MeV Neutron-Induced Damage in Si and SiC Power MOSFETs","authors":"Chao Peng;Hong Zhang;Zhangang Zhang;Teng Ma;Zhizhe Wang;Zhifeng Lei","doi":"10.1109/TED.2025.3588129","DOIUrl":"https://doi.org/10.1109/TED.2025.3588129","url":null,"abstract":"The comparison of the single event burnout (SEB) performance between 900-V Si and silicon carbide (SiC) MOSFETs is conducted using 14-MeV neutron irradiation. A SEB is observed for the Si MOSFET biased at 83% of the rated voltage, while no SEB occurs for the SiC MOSFET biased at 94% of the rated voltage. For the 900-V class power MOSFET, the planar SiC device seems more SEB hardened than the Si planar super-junction device. The linear energy transfer (LET) values and ranges of the secondary ions produced by the nuclear reaction of 14-MeV neutrons are obtained for Si and SiC devices. The maximum LET value of the secondary ions induced by 14-MeV neutrons can reach 9.85 MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm2/mg in the SiC device, which is high enough to induce SEB according to the previous heavy ion irradiation data. The mechanisms by which relatively low-energy neutrons are unable to induce SEB are related to the low range of the secondary ions. Most of the secondary ions have a range of less than <inline-formula> <tex-math>$3~mu $ </tex-math></inline-formula>m. It is interesting to note that the SEB damages caused by 14-MeV neutrons in Si devices are located in the transition region between the cell area and the gate pad, which means that this region is more sensitive to SEB than the cell region for super-junction Si MOSFETs. This is verified by the TCAD simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5104-5110"},"PeriodicalIF":3.2,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel SCR Topology of Embedded Bipolar Transistor With High-Holding Voltage and High-Temperature Tolerance for ESD Protection 一种用于ESD保护的高保持电压和耐高温嵌入式双极晶体管的新型可控硅拓扑结构

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-16 DOI: 10.1109/TED.2025.3586260

Yujie Liu;Yang Wang;Ke Zhang;Jian Yang;Xiangliang Jin

引用次数: 0