IEEE Transactions on Electron Devices最新文献

{"title":"Surface-Relief-Treated 940-nm VCSELs for High Beam Quality in Proximity Sensing","authors":"Yu-Ying Chen;Yuan-He Cai;Hua-Xin Xiong;Yi-Feng Huang;Li-Hong Zhu;Wei-Jie Guo;Yi-Jun Lu;Hao-Chung Kuo;Zhong Chen;Ting-Zhu Wu","doi":"10.1109/TED.2026.3713123","DOIUrl":"https://doi.org/10.1109/TED.2026.3713123","url":null,"abstract":"We designed, fabricated, and characterized a high-performance 940-nm vertical-cavity surface-emitting laser (VCSEL) that incorporates a surface-relief (SR) structure to enhance beam quality and maintain modal stability. The SR aperture was optimized through optical-electro simulations to suppress higher order transverse modes via locally reducing reflectivity at the aperture periphery while maintaining low threshold current and high power. The fabricated VCSEL exhibits a low threshold current of <inline-formula> <tex-math>$2sim 2.1$ </tex-math></inline-formula> mA and delivers <inline-formula> <tex-math>$19.4sim 20.5$ </tex-math></inline-formula> mW of maximum output power under <inline-formula> <tex-math>$33sim 34$ </tex-math></inline-formula>-mA continuous-wave (CW) operation. Far-field measurements confirm a significantly reduced beam divergence of 12.9° under 10 mA, with a quasi-Gaussian profile indicative of robust fundamental mode confinement. These results highlight the potential of SR-treated VCSELs for compact, high-precision photonic applications such as proximity sensing in next-generation devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5591-5597"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Structural Design of GaN MIS-HEMTs for Low-Earth-Orbit Radiation Hardness: Integrating Back-Barrier and Deep Source Via","authors":"Chenrui Zhang;Yixu Yao;Sen Huang;Li Yu;Hongtu Qian;Yi Pei;Qimeng Jiang;Zhaofu Zhang;Ke Wei;Xinhua Wang;Xinyu Liu","doi":"10.1109/TED.2026.3712325","DOIUrl":"https://doi.org/10.1109/TED.2026.3712325","url":null,"abstract":"A back-barrier and deep source via (BB and DSV) architecture is proposed to enhance the single-event burnout (SEB) robustness of gallium nitride high-electron-mobility transistors (GaN HEMTs), specifically targeting low-Earth-orbit (LEO) applications. SEB, a critical reliability concern, is triggered when radiation-induced holes accumulate beneath the gate dielectric in the <sc>off</small> state. In this work, heavy-ion irradiation using Ar ions (linear energy transfer (LET) <inline-formula> <tex-math>$approx15$ </tex-math></inline-formula> MeV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm<inline-formula> <tex-math>${}^{{2}}cdot $ </tex-math></inline-formula>mg<inline-formula> <tex-math>${}^{-{1}}text {)}$ </tex-math></inline-formula>—representative of the dominant particle spectrum in LEO—demonstrates the efficacy of the proposed design. By integrating an AlGaN graded back-barrier (BB) with a deep source via (DSV), the BB and DSV structure electrically pins the BB potential, creating a low-impedance path for rapid hole extraction. This mechanism significantly suppresses the transient field distortion that leads to burnout. Experimental results confirm a substantial increase in SEB threshold voltage (<inline-formula> <tex-math>${V}_{text {SEB}}text {)}$ </tex-math></inline-formula> from ~150 V in the control device to 600 V for the BB and DSV device. Furthermore, the design maintains dynamic performance by eliminating floating-body effects. This work offers a promising solution targeting the dominant low-LET particle spectrum encountered during LEO missions, effectively balancing device performance and reliability for commercial space applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5335-5341"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanism Investigation of Thermally Activated Lanthanum Diffusion in Dipole-Last Gate-Stacks","authors":"Yang Liu;Hong-Mei Zhang;Yuchun Li;Shaofeng Yu;Xiaona Zhu;Wei David Zhang","doi":"10.1109/TED.2026.3712302","DOIUrl":"https://doi.org/10.1109/TED.2026.3712302","url":null,"abstract":"In this study, La-dipole-inserted HfO2/SiO2 MOS capacitors were fabricated via a dipole-last process, with postcapping annealing (PCA) applied at varied temperatures to activate La dipoles. The thermal processing condition critically determines device performance by regulating La diffusion and oxygen redistribution in the gate stack. Scanning transmission electron microscopy-energy dispersive X-ray spectroscopy (STEM-EDX) confirms the gradual diffusion of La dipoles upon PCA temperature elevation, and X-ray photoelectron spectroscopy (XPS) verifies the formation of lanthanum silicate after thermal treatment. PCA temperature significantly modulates the flat-band voltage (<inline-formula> <tex-math>${V}_{textit {fb}}text {)}$ </tex-math></inline-formula> shift: residual La dipoles at the HfO2/TiN interface induce a positive <inline-formula> <tex-math>${V}_{textit {fb}}$ </tex-math></inline-formula> shift of ~70 mV at <inline-formula> <tex-math>$750~^{circ }$ </tex-math></inline-formula>C, while a conventional negative <inline-formula> <tex-math>${V}_{textit {fb}}$ </tex-math></inline-formula> shift occurs at <inline-formula> <tex-math>$880~^{circ }$ </tex-math></inline-formula>C. Further heating to <inline-formula> <tex-math>$1000~^{circ }$ </tex-math></inline-formula>C drives thorough La diffusion toward the HfO2/SiO2 interface, forming substantial lanthanum silicate and yielding a large negative <inline-formula> <tex-math>${V}_{textit {fb}}$ </tex-math></inline-formula> shift of ~350 mV. The contradictory <inline-formula> <tex-math>${V}_{textit {fb}}$ </tex-math></inline-formula> polarities at low and high PCA temperatures stem from temperature-dependent La distribution, which alters the valence-band offset (VBO). With increasing PCA temperature, the interface trap density (<inline-formula> <tex-math>${D}_{textit {it}}text {)}$ </tex-math></inline-formula> declines continuously, reaching a maximum reduction of 87% at <inline-formula> <tex-math>$1000~^{circ }$ </tex-math></inline-formula>C due to effective La dipole incorporation. The introduced La dipoles also suppress gate leakage up to one order of magnitude via oxygen vacancy compensation at <inline-formula> <tex-math>$750~^{circ }$ </tex-math></inline-formula>C. This work reveals that precise thermal budget control is essential for synergistically optimizing V modulation, leakage performance, and interfacial quality in dipole-last-processed gate stacks.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5577-5582"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved Interface Quality in β-Ga2O3 MOSFETs With a Crystalline (AlGa)2O3Cap","authors":"Xiaole Jia;Shuqi Huang;Yibo Wang;Bochang Li;Cizhe Fang;Haodong Hu;Zhengdong Luo;Yan Liu;Yue Hao;Genquan Han","doi":"10.1109/TED.2026.3716668","DOIUrl":"https://doi.org/10.1109/TED.2026.3716668","url":null,"abstract":"This work demonstrates <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 metal-oxide-semiconductor (MOS) devices with a crystalline (AlGa)2O3 cap formed by thin Al2O3 predeposition and postdeposition annealing (PDA). The cap effectively passivates interface defects and improves the overall gate-stack quality. Compared with control devices, the capped <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 MOS field-effect transistors (MOSFETs) show reduced hysteresis, improved subthreshold swing, enhanced current density, lower <sc>off</small>-state leakage, and improved breakdown, yielding a 42.7% enhancement in power figure of merit (PFOM). Reduced threshold-voltage shift under positive gate-bias stress further confirms suppressed electron trapping, highlighting crystalline (AlGa)2O3 cap engineering as an effective approach for improving <inline-formula> <tex-math>$beta $ </tex-math></inline-formula>-Ga2O3 MOS interface quality and device performance.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5862-5866"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"GaN Vertical Trench MOSFET With Gate Trench Recovery Using Stepped-Power Slanted Etching","authors":"Dawei Wang;Bingcheng Da;Junzhe Xie;Xianzhi Wei;Shisong Luo;Zonghao Zhang;Yuji Zhao;Houqiang Fu","doi":"10.1109/TED.2026.3713111","DOIUrl":"https://doi.org/10.1109/TED.2026.3713111","url":null,"abstract":"In this work, a new easy-to-implement etching damage recovery technique for the trench sidewall in gallium nitride (GaN) vertical trench MOSFETs, named stepped-power slanted reactive ion etching (SP-SRIE), was proposed. The device with SP-SRIE treatment shows improved channel properties and electrical characteristics compared with those without treatment due to the recovered etched gate trench surfaces. A channel mobility of 49 cm2/V <inline-formula> <tex-math>$cdot $ </tex-math></inline-formula> s, a breakdown voltage of 478 V, and an <sc>on</small>-resistance of 1.88 m<inline-formula> <tex-math>$Omega ~cdot $ </tex-math></inline-formula> cm2 were achieved. This work provides an effective alternative route for the future development of high-performance vertical GaN power trench MOSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5854-5857"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigations on Surge Current Capability and Failure Mechanism of SiC MOSFETs in Third Quadrant","authors":"Zixuan Ye;Xiaochuan Deng;Haohao Dai;Xing Zeng;Hexin Zhu;Xu Li;Xuan Li;Bo Zhang","doi":"10.1109/TED.2026.3714364","DOIUrl":"https://doi.org/10.1109/TED.2026.3714364","url":null,"abstract":"In this article, the surge current capability and failure mechanism of double trench-gate and planar-gate SiC MOSFETs (DT-MOS and P-MOS) in the third quadrant (including channel turn-on and channel turn-off mode) are investigated. The maximum surge peak of double trench-gate SiC MOSFET (DT-MOS) reaches 38 and 63 A in channel turn-on mode (gate voltage of +15 V) and channel turn-off mode (gate voltage of −5 V), respectively. The surge current capability of DT-MOS in channel turn-on mode has decreased by 41.6% compared with channel turn-off mode. However, the maximum surge peak of planar-gate SiC MOSFET (P-MOS) is found to be similar in channel turn-on mode and turn-off mode (78 and 76 A). A similar failure phenomenon for P-MOS occurs under two different gate–source biases by decapsulation analysis. This is because the excessive temperature in P-MOS under surge current events produces the melting of wire or metal layers and gate–source short. Whereas, DT-MOS exhibits a distinctive difference in failure mechanism after the surge stress at a gate voltage of +15 V. The distinct localized burnout spot has been observed in the transition region of the failed device. Finite element simulation and equivalent circuit analysis indicate that the transition region conducts 14% of the total surge current in the channel turn-on mode, whereas that of the channel turn-off mode is only 5.9%. Due to the limited area of the transition region, the excessive transition current density triggers thermal runaway and localized burnout, degrading the surge current capability of DT-MOS in the channel turn-on mode.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5460-5465"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Optimized Process Variation Simulation Framework for Nanoscale Semiconductor Device by Improved 3-D Quantum-Corrected Carrier Transport Simulation Method","authors":"Yiqun Niu;Wenchao Chen;Liang Tian;Qinyi Huang;Yizhang Liu;Linsheng Wu;Jun-Fa Mao","doi":"10.1109/TED.2026.3714376","DOIUrl":"https://doi.org/10.1109/TED.2026.3714376","url":null,"abstract":"Downscaling of the device dimensions amplifies the impact of process variations on the characteristics of a nanoscale semiconductor device. The conventional process variation simulation framework requires hundreds of remeshing and carrier transport simulation instances per statistical parameter set of process variation analysis, which suffers from two limitations: 1) mesh generation from complex geometries produces meshing grids with high skewness and nonorthogonality, which degrades simulation accuracy and 2) repeated remeshing operations incur expensive computational cost. Thus, in this article, an optimized process variation simulation framework is proposed to simultaneously improve the computational efficiency while maintaining high accuracy on the low-quality meshes generated in complex geometries. The optimized simulation framework replaces the remeshing operation with a mesh remapping strategy and employs an improved carrier transport simulation method to address numerical inaccuracies in the low-quality meshing grids generated during mesh remapping operations. The improved 3-D carrier transport simulation method is first validated against experimental data on a nominal FinFET structure. Furthermore, by performing carrier transport simulations on both traditionally remeshed grids and remapped grids, the results demonstrate that our improved method effectively compensates for the accuracy loss caused by the lower quality meshes inherent to the remapping strategy. Finally, the feasibility and efficiency of the optimized simulation framework for process variation analysis are demonstrated through a study on line-edge roughness (LER) in UTB-FinFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5413-5419"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling of Electrochromic Devices: A Physics-Based Equivalent Circuit Approach","authors":"S. J. Alankrith;Tanushree H. Choudhury;Revathy Padmanabhan","doi":"10.1109/TED.2026.3716201","DOIUrl":"https://doi.org/10.1109/TED.2026.3716201","url":null,"abstract":"Electrochromic (EC) devices have a wide range of applications due to their electrically tunable optical properties, and equivalent circuit models facilitate the simulation of large arrays of EC devices and systems. However, conventional equivalent circuit models for EC devices mostly adopt an empirical approach, thereby not capturing the underlying physical processes; whereas, physics-based models give detailed physical insight but have limited scalability when modeling large arrays. Therefore, in this work, we have developed a physics-based equivalent circuit model to capture the diffusion process inside the EC layer (governed by Fick’s second law of diffusion), equilibrium potential at the EC–electrolyte interface (derived from the regular solution model), and the charge transfer process (with the Butler–Volmer equation), using different circuit elements. The model captures the cyclic voltammetry (CV), chronoamperometry (CA), and transmittance modulation characteristics of EC devices. The simulation results were validated with experimental measurements shown in this work and data reported in the literature as well. The proposed physics-based equivalent circuit model captures the optical response of EC devices, providing insight into the design and optimization of large array EC devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5403-5412"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IEEE Transactions on Electron Devices Publication Information","authors":"","doi":"10.1109/TED.2026.3723701","DOIUrl":"https://doi.org/10.1109/TED.2026.3723701","url":null,"abstract":"","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"C2-C2"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11682809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Responsivity ReMoS2 Photodetector on Gallium Nitride Patterned Substrate for Visible-Light Image Sensing and Communication Applications","authors":"Bing Jiang;Jun He;Jiachang Guo;Xue Fan;Chengcan Chen;Yunfang Wang;Xiaohua Li;Hezhou Liu;Xinke Liu","doi":"10.1109/TED.2026.3718846","DOIUrl":"https://doi.org/10.1109/TED.2026.3718846","url":null,"abstract":"In this work, a ReMoS2 2-D material was grown on a sapphire planar substrate (FS) by chemical vapor deposition (CVD), and transferred to a gallium nitride patterned substrate (PGS) by a wet-transfer process to prepare ReMoS2/FS and ReMoS2/PGS photodetectors. Compared with the performance of the ReMoS2/FS photodetector, the <inline-formula> <tex-math>${I}_{mathbf {light}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{mathbf {dark}}$ </tex-math></inline-formula> of the ReMoS2/PGS photodetector is <inline-formula> <tex-math>${1.35} times {10}^{{3}}$ </tex-math></inline-formula>, the responsivity is 91 A/W, and the detectivity is <inline-formula> <tex-math>${4.1} times {10}^{{10}}$ </tex-math></inline-formula> Jones under the irradiation of light with a wavelength of 460 nm, which are increased by 46, 56, and 151 times, respectively. At the same time, the ReMoS2/PGS photodetector also has imaging capability and communication function.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5646-5651"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}