IEEE Transactions on Electron Devices最新文献_第7页

Layout Optimization of Dual-Directional SCR for Holding Voltage Equilibrium in ESD Applications ESD应用中保持电压平衡的双向可控硅布局优化

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3558487

Feibo Du;Ruibo Chen;Yi Liu;Fei Hou;Xiaoyu Dong;Dongxing Gao;Jiaqiang Zheng;Zihan Zheng;Yimu Yang;Xuyao Wang;Zhiwei Liu

引用次数: 0

2-D Hydrodynamic Simulation of TeraFETs Beyond the Gradual-Channel Approximation for Transient, Large-Signal, or Ultrahigh-Frequency Simulations 2-D流体动力学模拟的TeraFETs超越渐近通道近似瞬态，大信号，或超高频模拟

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3558157

Florian Ludwig;Hartmut G. Roskos;Raul Borsche

{"title":"2-D Hydrodynamic Simulation of TeraFETs Beyond the Gradual-Channel Approximation for Transient, Large-Signal, or Ultrahigh-Frequency Simulations","authors":"Florian Ludwig;Hartmut G. Roskos;Raul Borsche","doi":"10.1109/TED.2025.3558157","DOIUrl":"https://doi.org/10.1109/TED.2025.3558157","url":null,"abstract":"In the past decade, detection of THz radiation by plasma-wave-assisted mixing in antenna-coupled field-effect transistors (TeraFETs)—implemented in various semiconductor material systems (Si CMOS, GaN/AlGaN, GaAs/AlGaAs, and graphene)—has matured and led to a practically applied detector technology. This has been supported by the development of powerful device simulation tools which take into account relevant collective carrier dynamics and mixing processes in various approximations. These tools mostly model carrier transport in one-dimension (1-D) and they are usually geared toward continuous-wave illumination of the device and small-signal response. Depending on their implementation, it may not be possible readily to simulate large-signal and pulsed operation. Another approximation which may lead to unsatisfactory results is the 1-D restriction to calculate only the longitudinal electric field components. Especially at the edges of the gate electrode, solving of the 2-D Poisson equation promises better results. This contribution introduces a stable way to solve the 2-D Poisson equation self-consistently with the hydrodynamic transport equations including the numerically challenging convection term. We employ a well-balanced approximate Harten-Lax-van-Leer-Contact (HLLC) Riemann solver. The approach is well suited for the future treatment of transient and large-signal cases. The 2-D treatment also generically extends the model beyond the gradual-channel approximation and allows to calculate the FET’s response at high THz frequencies where the gate-to-channel potential acquires a nonlocal character. Model calculations are performed for the exemplary case of a 65-nm Si CMOS TeraFET in the isothermal approximation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"3090-3098"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10965757","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of Back-Gate Bias on the Total Ionizing Dose and Hot Carrier Injection Effects in Double SOI nMOSFETs 双SOI nmosfet中后门偏压对总电离剂量和热载流子注入效应的影响

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3552744

Yuan Gao;Zihan Wang;Yongwei Chang;Zhongying Xue;Xing Wei

{"title":"Impact of Back-Gate Bias on the Total Ionizing Dose and Hot Carrier Injection Effects in Double SOI nMOSFETs","authors":"Yuan Gao;Zihan Wang;Yongwei Chang;Zhongying Xue;Xing Wei","doi":"10.1109/TED.2025.3552744","DOIUrl":"https://doi.org/10.1109/TED.2025.3552744","url":null,"abstract":"Double silicon-on-insulator (DSOI) device exhibits high tolerance to total ionizing dose (TID) effect due to back gate bias (<inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>) modulation. Negative <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the performance degradation caused by the TID effect, while positive <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the degradation caused by hot carrier injection (HCI) effect. This article focuses on the synergistic effect between TID and HCI under different back-gate voltage and modulation effect of <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>. The HCI effect is exacerbated by TID effect owing to the trapped charges in the oxide, which enhance the impact of ionizing in channel region. <inline-formula> <tex-math>${Delta } {V}_{text {th}}$ </tex-math></inline-formula> [<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> at 3 Mrad(Si) <inline-formula> <tex-math>$- {V}_{text {th}}$ </tex-math></inline-formula> at 0 Mrad(Si)] of DSOI MOSFET without stress is approximately −0.215 V, larger than that of stressed device. Additionally, applying a back-gate bias to mid-Si is an effective method to suppress the degradation in synergistic experiments.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2159-2164"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploiting Quasi-Volatility in Silver-Doped RRAMs for Physical Unclonable Functions Toward Robust Security Primitives 利用掺银rram的准挥发性实现物理不可克隆函数的鲁棒安全原语

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3556101

Guobin Zhang;Zhen Wang;Qi Luo;Bin Yu;Can Li;Qing Wan;Yishu Zhang

{"title":"Exploiting Quasi-Volatility in Silver-Doped RRAMs for Physical Unclonable Functions Toward Robust Security Primitives","authors":"Guobin Zhang;Zhen Wang;Qi Luo;Bin Yu;Can Li;Qing Wan;Yishu Zhang","doi":"10.1109/TED.2025.3556101","DOIUrl":"https://doi.org/10.1109/TED.2025.3556101","url":null,"abstract":"Resistance random access memory (RRAM)-based physical unclonable functions (PUFs) have emerged as promising security primitives owing to their ability to generate reliable, unpredictable maps. In this study, we propose a novel PUF architecture that leverages the quasi-volatility of temporal and spatial randomness in a <inline-formula> <tex-math>$32times 32$ </tex-math></inline-formula> crossbar array composed of silver-doped RRAM devices. The proposed PUF constructs a unique identifier based on the intrinsic switching variability and temporal retention characteristics of the RRAM devices. This dual source of randomness ensures high unpredictability and robustness against environmental noise and common modeling attacks. In optimized experiments, the PUF achieved uniformity, inter-hamming distance (inter-HD), and intra-hamming distance (intra-HD) metrics of 49.9%, 50.11%, and 0%, respectively, demonstrating strong stability and resistance to bit errors. The architecture incorporates a temporal majority voting (TMV) scheme to correct bit errors without additional hardware, achieving a bit error rate (BER) of 0%. These results highlight the potential of this RRAM-based PUF for secure key and identification-generation applications, especially in demanding internet of things (IoT) and embedded systems. Future work will focus on further evaluating the resilience against advanced attacks and integrating the PUF into complete security systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2347-2353"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of TID and DD Effects on FD SOI Nanowire FET Induced by Proton Irradiation 质子辐照诱导FD SOI纳米线场效应管的TID和DD效应研究

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3558489

Dabok Lee;Jonghyeon Ha;Minki Suh;Minsang Ryu;Mikaël Cassé;Sergio Nicoletti;Dae-Young Jeon;Jungsik Kim

引用次数: 0

A Compact Model for Degradation Behaviors in Hf0.2Zr0.8O2 Anti-Ferroelectric Devices Hf0.2Zr0.8O2反铁电器件退化行为的紧凑模型

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3558484

Lijian Chen;Yaru Ding;Zeping Weng;Jianguo Li;Daolin Cai;Yi Zhao

引用次数: 0

Tailoring Ferroelectric Performance and Domain Structure Ordering in HZO Capacitors via 2D-WS2 Multifunctional Layer 基于2D-WS2多功能层的HZO电容器铁电性能和畴结构排序

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-15 DOI: 10.1109/TED.2025.3553822

Seungkwon Hwang;Hojung Jang;Kyumin Lee;Laeyong Jung;Jongwon Yoon;Jung-Dae Kwon;Kyung Song;Yonghun Kim;Hyunsang Hwang

{"title":"Tailoring Ferroelectric Performance and Domain Structure Ordering in HZO Capacitors via 2D-WS2 Multifunctional Layer","authors":"Seungkwon Hwang;Hojung Jang;Kyumin Lee;Laeyong Jung;Jongwon Yoon;Jung-Dae Kwon;Kyung Song;Yonghun Kim;Hyunsang Hwang","doi":"10.1109/TED.2025.3553822","DOIUrl":"https://doi.org/10.1109/TED.2025.3553822","url":null,"abstract":"In this study, we propose a high-performance and reliable ferroelectric capacitor based on Hfx <inline-formula> <tex-math>$Zr_{{1}-{x}}$ </tex-math></inline-formula>O2 (HZO) integrated with an ultrathin multifunctional 2D-WS2 layer. The WS2 layer, positioned at the interface between the bottom electrode and HZO, serves a multiple function. First, the WS2 acts as a protective layer, effectively suppressing the formation of interfacial defects, such as oxygen vacancies and dead layers during the device fabrication process. Second, this layer functions as a seed layer, promoting the growth of vertically aligned HZO domain structures and enhancing the ferroelectric crystallinity of HZO. This approach addresses key limitations in conventional HZO, including interfacial instability, random domain distribution, and inconsistent switching behavior. Our experimental results reveal significant improvements in ferroelectric performance, achieving stable endurance exceeding <inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula> cycles while maintaining a high remanent polarization (<inline-formula> <tex-math>$2P_{text {r}} gt 50~mu $ </tex-math></inline-formula> <inline-formula> <tex-math>$C/cm^{{2}}$ </tex-math></inline-formula>). Additionally, long-term retention performance is expected to exceed ten years at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C. Furthermore, the integration of a WS2 interface layer demonstrates excellent device-to-device uniformity and consistency, even in nanoscale HZO device structures. This work provides new insights into the development of high-performance ferroelectric nonvolatile memory technology by highlighting the multiple advantages of the WS2 layer, which enhances interface stability and facilitates vertical domain alignment.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2700-2707"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection 铁电在栅极侧注入铁电场效应管内存窗口扩展中的作用

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-14 DOI: 10.1109/TED.2025.3552013

Yixin Qin;Saikat Chakraborty;Zijian Zhao;Sizhe Ma;Moonyoung Jung;Kijoon Kim;Suhwan Lim;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni

{"title":"Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection","authors":"Yixin Qin;Saikat Chakraborty;Zijian Zhao;Sizhe Ma;Moonyoung Jung;Kijoon Kim;Suhwan Lim;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni","doi":"10.1109/TED.2025.3552013","DOIUrl":"https://doi.org/10.1109/TED.2025.3552013","url":null,"abstract":"In this work, we present a comprehensive experimental and modeling study to clarify the role of the ferroelectric (FE) layer in enhancing the memory window (MW) of FeFETs with gate-side charge injection. We separated the FE contributions to the MW into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: 1) FE layer expands the MW in two ways: by enhanced FE polarization induced by gate-side charge trapping into the CTL and through their superlinear <inline-formula> <tex-math>${Q} {_{text {FE}}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>${V} {_{text {FE}}}$ </tex-math></inline-formula> relationship that boosts the CTL electric field and enhances charge trapping; 2) the contributions from polarization and CTL trapping mutually reinforce each other, resulting in a larger MW compared to a FE + dielectric stack or a high-<inline-formula> <tex-math>${k} +$ </tex-math></inline-formula> CTL stack, where, in both stacks, only one factor is active; 3) enhanced polarization strengthens the channel interfacial layer electric field, suppressing electron detrapping from the channel and, thus, enabling immediate read-after–write, thereby improving FeFET read throughput; and 4) the MW can be further increased incorporating a blocking oxide layer above the CTL, achieving a 12-V window with a 2-nm-thick Al2O3 layer.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2708-2715"},"PeriodicalIF":2.9,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Operation Voltage Reduction of Silicon Based Light Sources by Surface Texturing 基于表面纹理的硅基光源工作电压降低

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-10 DOI: 10.1109/TED.2025.3556107

O. Pérez-Díaz;A. A. González- Fernández;D. Estrada-Wiese;M. Aceves-Mijares

{"title":"Operation Voltage Reduction of Silicon Based Light Sources by Surface Texturing","authors":"O. Pérez-Díaz;A. A. González- Fernández;D. Estrada-Wiese;M. Aceves-Mijares","doi":"10.1109/TED.2025.3556107","DOIUrl":"https://doi.org/10.1109/TED.2025.3556107","url":null,"abstract":"Silicon-rich oxide (SRO) light-emitting capacitors (LECs) have proven to be good candidates to be monolithically integrated in electrophotonic (Eph) circuits due to their complementary metal-oxide–semiconductor (CMOS) fabrication compatibility and broadband emission spectra. However, their relatively high operating voltage (i.e., the voltage required to emit detectable light) limits their use in applications where portability and low energy consumption are imperative. Among the strategies to overcome this problem, the interlayering of SRO films with different electrical and light-emitting properties has been explored besides the use of metal-assisted chemical etching (MACE)-textured Si substrates to improve carrier injection into the active material. In this study, a combination of both the strategies is analyzed by fabricating LECs featuring SRO multilayer (ML) structures on top of Si textured substrates to reduce the operating voltage of the LECs even farther. The textured Si surfaces were studied to determine an improved arrangement of different SRO layers to ensure complete coverage of Si peaks formed during texturing of the substrate. For comparison, the same LEC structures were fabricated on polished substrates showing an increased operating voltage of around <inline-formula> <tex-math>${V} _{text {op}} =50$ </tex-math></inline-formula> V in contrast to the new proposed LECs, which presented light emission at only <inline-formula> <tex-math>${V} _{text {op}} =15$ </tex-math></inline-formula> V. These results open promising application opportunities to monolithically integrate Si-based light emitters in photonic and electronic devices and circuits.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2179-2186"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultralow Contact Resistivity of <0.13 Ω · mm for Normal Ti/Al/Ni/Au Ohmic Contact on Non-Recessed i-AlGaN/GaN 非凹槽i-AlGaN/GaN上正常Ti/Al/Ni/Au欧姆接触的超低接触电阻率<0.13 Ω·mm

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-04-10 DOI: 10.1109/TED.2025.3555265

Xiao Wang;Zhiyu Lin;Yumin Zhang;Jianfeng Wang;Ke Xu

引用次数: 0