IEEE Transactions on Electron Devices最新文献

{"title":"A Compact Model for Degradation Behaviors in Hf0.2Zr0.8O2 Anti-Ferroelectric Devices","authors":"Lijian Chen;Yaru Ding;Zeping Weng;Jianguo Li;Daolin Cai;Yi Zhao","doi":"10.1109/TED.2025.3558484","DOIUrl":"https://doi.org/10.1109/TED.2025.3558484","url":null,"abstract":"A compact model is developed to describe degradation behaviors of the polarization-voltage (P–V) and current-voltage (I–V) characteristics in Hf0.2Zr0.8O2 (HZO) anti-ferroelectric (AFE) capacitors. It is confirmed that, during field cycling, the evolution of both P–V and I–V characteristics follows the similar rule related to the Kohlrausch-Williams/Watts (KWWs) random-walk relaxation behavior of the switching polarization. The opposite but similar behavior of voltage shift in both characteristics suggests that charge injection should be an underlying mechanism for the observed polarization imprint. The degradation is attributed to the increasing charge defects at the interface between interfacial layer (IL) and the electrode.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 6","pages":"2936-2942"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tailoring Ferroelectric Performance and Domain Structure Ordering in HZO Capacitors via 2D-WS2 Multifunctional Layer","authors":"Seungkwon Hwang;Hojung Jang;Kyumin Lee;Laeyong Jung;Jongwon Yoon;Jung-Dae Kwon;Kyung Song;Yonghun Kim;Hyunsang Hwang","doi":"10.1109/TED.2025.3553822","DOIUrl":"https://doi.org/10.1109/TED.2025.3553822","url":null,"abstract":"In this study, we propose a high-performance and reliable ferroelectric capacitor based on Hfx <inline-formula> <tex-math>$Zr_{{1}-{x}}$ </tex-math></inline-formula>O2 (HZO) integrated with an ultrathin multifunctional 2D-WS2 layer. The WS2 layer, positioned at the interface between the bottom electrode and HZO, serves a multiple function. First, the WS2 acts as a protective layer, effectively suppressing the formation of interfacial defects, such as oxygen vacancies and dead layers during the device fabrication process. Second, this layer functions as a seed layer, promoting the growth of vertically aligned HZO domain structures and enhancing the ferroelectric crystallinity of HZO. This approach addresses key limitations in conventional HZO, including interfacial instability, random domain distribution, and inconsistent switching behavior. Our experimental results reveal significant improvements in ferroelectric performance, achieving stable endurance exceeding <inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula> cycles while maintaining a high remanent polarization (<inline-formula> <tex-math>$2P_{text {r}} gt 50~mu $ </tex-math></inline-formula> <inline-formula> <tex-math>$C/cm^{{2}}$ </tex-math></inline-formula>). Additionally, long-term retention performance is expected to exceed ten years at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C. Furthermore, the integration of a WS2 interface layer demonstrates excellent device-to-device uniformity and consistency, even in nanoscale HZO device structures. This work provides new insights into the development of high-performance ferroelectric nonvolatile memory technology by highlighting the multiple advantages of the WS2 layer, which enhances interface stability and facilitates vertical domain alignment.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2700-2707"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection","authors":"Yixin Qin;Saikat Chakraborty;Zijian Zhao;Sizhe Ma;Moonyoung Jung;Kijoon Kim;Suhwan Lim;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni","doi":"10.1109/TED.2025.3552013","DOIUrl":"https://doi.org/10.1109/TED.2025.3552013","url":null,"abstract":"In this work, we present a comprehensive experimental and modeling study to clarify the role of the ferroelectric (FE) layer in enhancing the memory window (MW) of FeFETs with gate-side charge injection. We separated the FE contributions to the MW into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: 1) FE layer expands the MW in two ways: by enhanced FE polarization induced by gate-side charge trapping into the CTL and through their superlinear <inline-formula> <tex-math>${Q} {_{text {FE}}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>${V} {_{text {FE}}}$ </tex-math></inline-formula> relationship that boosts the CTL electric field and enhances charge trapping; 2) the contributions from polarization and CTL trapping mutually reinforce each other, resulting in a larger MW compared to a FE + dielectric stack or a high-<inline-formula> <tex-math>${k} +$ </tex-math></inline-formula> CTL stack, where, in both stacks, only one factor is active; 3) enhanced polarization strengthens the channel interfacial layer electric field, suppressing electron detrapping from the channel and, thus, enabling immediate read-after–write, thereby improving FeFET read throughput; and 4) the MW can be further increased incorporating a blocking oxide layer above the CTL, achieving a 12-V window with a 2-nm-thick Al2O3 layer.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2708-2715"},"PeriodicalIF":2.9,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Operation Voltage Reduction of Silicon Based Light Sources by Surface Texturing","authors":"O. Pérez-Díaz;A. A. González- Fernández;D. Estrada-Wiese;M. Aceves-Mijares","doi":"10.1109/TED.2025.3556107","DOIUrl":"https://doi.org/10.1109/TED.2025.3556107","url":null,"abstract":"Silicon-rich oxide (SRO) light-emitting capacitors (LECs) have proven to be good candidates to be monolithically integrated in electrophotonic (Eph) circuits due to their complementary metal-oxide–semiconductor (CMOS) fabrication compatibility and broadband emission spectra. However, their relatively high operating voltage (i.e., the voltage required to emit detectable light) limits their use in applications where portability and low energy consumption are imperative. Among the strategies to overcome this problem, the interlayering of SRO films with different electrical and light-emitting properties has been explored besides the use of metal-assisted chemical etching (MACE)-textured Si substrates to improve carrier injection into the active material. In this study, a combination of both the strategies is analyzed by fabricating LECs featuring SRO multilayer (ML) structures on top of Si textured substrates to reduce the operating voltage of the LECs even farther. The textured Si surfaces were studied to determine an improved arrangement of different SRO layers to ensure complete coverage of Si peaks formed during texturing of the substrate. For comparison, the same LEC structures were fabricated on polished substrates showing an increased operating voltage of around <inline-formula> <tex-math>${V} _{text {op}} =50$ </tex-math></inline-formula> V in contrast to the new proposed LECs, which presented light emission at only <inline-formula> <tex-math>${V} _{text {op}} =15$ </tex-math></inline-formula> V. These results open promising application opportunities to monolithically integrate Si-based light emitters in photonic and electronic devices and circuits.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2179-2186"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultralow Contact Resistivity of <0.13 Ω · mm for Normal Ti/Al/Ni/Au Ohmic Contact on Non-Recessed i-AlGaN/GaN","authors":"Xiao Wang;Zhiyu Lin;Yumin Zhang;Jianfeng Wang;Ke Xu","doi":"10.1109/TED.2025.3555265","DOIUrl":"https://doi.org/10.1109/TED.2025.3555265","url":null,"abstract":"By utilizing a traditional Ti/Al/Ni/Au metal stack on i-AlGaN/GaN, we achieved an ultralow contact resistivity of <inline-formula> <tex-math>$lt 0.13~Omega ~cdot $ </tex-math></inline-formula> mm through a combined annealing process, which includes holding at <inline-formula> <tex-math>$550~^{circ }$ </tex-math></inline-formula>C for 20 s, followed by a 60-s annealing at <inline-formula> <tex-math>$840~^{circ }$ </tex-math></inline-formula>C with an optimized ramp-up rate of <inline-formula> <tex-math>$10~^{circ }$ </tex-math></inline-formula>C/s. The formation of TixAlyAuz alloy spikes directly contacting the 2DEG is identified as the primary mechanism for the ultralow contact resistance, which we attribute to the severity of Al transitioning into a molten state during the process.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2246-2251"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Development of Polarization-Enhanced E-Mode GaN p-FET and Complementary Logic (CL) Circuits","authors":"Teng Li;Jingjing Yu;Sihang Liu;Yunhong Lao;Jiawei Cui;Hengyuan Qi;Junjie Yang;Han Yang;Xuelin Yang;Maojun Wang;Yamin Zhang;Shiwei Feng;Bo Shen;Meng Zhang;Jin Wei","doi":"10.1109/TED.2025.3556047","DOIUrl":"https://doi.org/10.1109/TED.2025.3556047","url":null,"abstract":"The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<inline-formula> <tex-math>${t}_{x}$ </tex-math></inline-formula>) is found to be a critical parameter that influences the device metrics. With a decrease in <inline-formula> <tex-math>${t}_{x}$ </tex-math></inline-formula> (i.e., larger recess depth), a more negative threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>) is achieved; however, the trade-off is an increase in <inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula>. The E-mode GaN p-FET with <inline-formula> <tex-math>${t}_{x} =32$ </tex-math></inline-formula> nm exhibits a <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> of −1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {off}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6.9times 10^{{7}}$ </tex-math></inline-formula>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> of 1.3 V and an <inline-formula> <tex-math>${R}_{text {on}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$6~mathrm {Omega cdot }$ </tex-math></inline-formula>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <inline-formula> <tex-math>${V}_{text {DD}} =6$ </tex-math></inline-formula> V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2259-2264"},"PeriodicalIF":2.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millisecond Pulsed Light Annealing for Improving Performance of Top-Gate Self-Aligned a-IGZO TFT","authors":"Heetae Kim;Seohak Park;Johak Jeong;Jun-Hwe Cha;Hoseok Lee;Chihun Sung;Jeho Na;Keun Heo;Sung Haeng Cho;Sung-Yool Choi;Byung Jin Cho","doi":"10.1109/TED.2025.3556116","DOIUrl":"https://doi.org/10.1109/TED.2025.3556116","url":null,"abstract":"The application of millisecond intense pulsed light (IPL) annealing to improve the electrical properties of top-gate self-aligned (TG-SA) amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) was investigated. The IPL annealing with a pulse energy of 40 J/cm2 and a pulsewidth of 20 ms resulted in 53.7% increase in <inline-formula> <tex-math>$mu _{text {FE}}$ </tex-math></inline-formula> and a 128.4% improvement in <inline-formula> <tex-math>${I}_{text {on}}$ </tex-math></inline-formula>, compared to the unannealed devices. These improvements are attributed to the selective improvement of the specific contact resistivity (<inline-formula> <tex-math>$rho _{text {c}}$ </tex-math></inline-formula>) by the IPL annealing. In addition, positive bias stress (PBS) reliability and temperature-dependent I–V measurements show the improved stability in the IPL-annealed devices and the lower activation energy (<inline-formula> <tex-math>${E}_{text {A}}$ </tex-math></inline-formula>) for charge transport, indicating that the channel region would also have a lower defect density and barrier height for carrier transport.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2399-2405"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144072966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and Accurate Prediction of Electrical Characteristics of Next-Generation Node 3-D NAND Flash Memory Using Transfer Learning","authors":"Hyundong Jang;Soomin Kim;Kyeongrae Cho;Kihoon Nam;Donghyun Kim;Hyeok Yun;Seungjoon Eom;Rock-Hyun Baek","doi":"10.1109/TED.2025.3556104","DOIUrl":"https://doi.org/10.1109/TED.2025.3556104","url":null,"abstract":"Electrical characteristics of scaled 3-D <sc>nand</small> cells for next-generation node development were predicted using transfer learning with limited data. The <sc>nand</small> cell structure parameters were considered as the inputs, and outputs included key electrical characteristics, such as cell <inline-formula> <tex-math>${V}_{t}$ </tex-math></inline-formula>, the difference in <inline-formula> <tex-math>${V}_{t}$ </tex-math></inline-formula> between the initial and programming states (<inline-formula> <tex-math>$Delta {V}_{t}$ </tex-math></inline-formula>), subthreshold swing (SS), and <sc>on</small>-current (<inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>). A multilayer perceptron (MLP) model comprising four hidden layers and focusing on large <sc>nand</small> cells (25 nm gate length) with 2000 data points served as a pre-trained model. The transfer model leveraged pre-trained knowledge to predict the electrical characteristics of smaller cells (19 nm gate length) with 500 data points without weight and bias training. Evaluation of test data exhibited remarkable accuracy with both the mean and standard deviation below 3%, proving the model’s effectiveness despite limited data. In addition, a comprehensive evaluation was conducted by comparing the performance of the model with variations in the dataset size and the presence of transfer learning, highlighting the effectiveness and advantages of transfer learning. Transfer learning could provide detailed structure information of the next node for engineers and expedite device development, resulting in significant time and cost savings.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2354-2359"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144073028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a Low-Loss Transmission Structure for W-Band TWT","authors":"Zhiyu Chen;Jingrui Duan;Yuan Zheng;Hao Li;Yubin Gong","doi":"10.1109/TED.2025.3556048","DOIUrl":"https://doi.org/10.1109/TED.2025.3556048","url":null,"abstract":"A low-loss transmission structure for W-band traveling wave tube (TWT) is proposed in this article. It converts the rectangular waveguide fundamental TE10 mode into the corrugate waveguide HE11 mode with a quasi-Gaussian energy distribution, thereby reducing ohmic loss on the waveguide walls. The sections maintaining and generating the HE11 mode are theoretically analyzed. The simulation results show that the <inline-formula> <tex-math>${S} _{{11}}$ </tex-math></inline-formula> of the converter is less than −20 dB in the frequency range of 80–100 GHz, and the mode conversion purity reaches 99.66%. Compared with a conventional rectangular waveguide with a 4.5 dB/m transmission loss, the insertion loss of novel structure has successfully been reduced by 3.1 dB/m to as low as 1.4 dB/m Furthermore, the same length W-band low-loss transmission structure and rectangular waveguide have been fabricated and cold-tested, the results reveal a reduction in insertion loss of 2.5 dB per meter, verifying the simulation predictions. A burned spot experiment was conducted to verify the energy distribution of the HE11 mode. The experimental results confirm the feasibility of the proposed low-loss transmission structure for low-loss transmission in W-band TWT input-output structures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2611-2617"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extremely High ESD Failure Voltage of RESURF LDMOS Devices for ESD Resilient Driver Applications","authors":"Aakanksha Mishra;M. Monishmurali;B. Sampath Kumar;Shaik Ahamed Suzaad;Shubham Kumar;Kiran Pote Sanjay;Amit Kumar Singh;Avinash Singh;Ankur Gupta;Mayank Shrivastava","doi":"10.1109/TED.2025.3556114","DOIUrl":"https://doi.org/10.1109/TED.2025.3556114","url":null,"abstract":"This work reports an extremely high ESD failure voltage in the transmission line pulse (TLP) characteristics of the laterally diffused metal-oxide-semiconductor (LDMOS) devices, while investigating a correlation between the critical voltage and filament formation. A high failure voltage enables an additional immunity to ESD damage by providing extra protection against the overvoltage stress in high-voltage (HV) I/O applications. The ESD behavior of LDMOS devices in the presence of reduced surface field (RESURF)-implant in the drift region is investigated in detail. Furthermore, an approach to drift region design and electric field engineering that affects this high failure voltage in RESURF LDMOS devices is discussed, using measurement and 3-D TCAD simulation.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2187-2194"},"PeriodicalIF":2.9,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}