IEEE Transactions on Electron Devices最新文献_第10页

Energy-Efficient CNN Accelerator Using Voltage-Gated DSHE-MRAM

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-11 DOI: 10.1109/TED.2025.3537592

Gaurav Verma;Sandeep Soni;Arshid Nisar;Seema Dhull;Brajesh Kumar Kaushik

{"title":"Energy-Efficient CNN Accelerator Using Voltage-Gated DSHE-MRAM","authors":"Gaurav Verma;Sandeep Soni;Arshid Nisar;Seema Dhull;Brajesh Kumar Kaushik","doi":"10.1109/TED.2025.3537592","DOIUrl":"https://doi.org/10.1109/TED.2025.3537592","url":null,"abstract":"Modern convolutional neural networks (CNNs) architectures need millions of parameters to be stored and computed in hardware for image classification. This needs a huge amount of memory and power in conventional hardware accelerator architectures. The concept of neuromorphic and in-memory computing (IMC) using emerging memory technologies has led to energy-efficient computations for hardware accelerators. This work presents a voltage-gated dual-bit spin Hall effect (VG-DSHE) magnetic random access memory (MRAM) device-based accelerator. The VG-DSHE-MRAM provides efficiency in terms of power and speed as compared to other MRAM devices. A crossbar array is implemented using VG-DSHE devices to exploit high-density storage, energy-efficiency, and fast multiply and accumulate (MAC) computation. Finally, a complete hardware implementation of CNN architecture is presented for image classification using the CIFAR-10 dataset without any significant accuracy degradation. The proposed VG-DSHE-based CNN accelerator is <inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula> more energy-efficient as compared to conventional differential spin Hall effect (DSHE)-based designs and achieves a throughput efficiency of 1.57, 0.49, 0.035, and 0.018 TSOPS/W for VGG8, VGG16, AlexNet, and ResNet18 architectures, respectively. Furthermore, the proposed accelerator is compared with other emerging memories for AlexNet architecture that shows <inline-formula> <tex-math>$181times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$14.76times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$2.4times $ </tex-math></inline-formula>, <inline-formula> <tex-math>$2.25times $ </tex-math></inline-formula>, and <inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula> improvement in crossbar power consumption as compared to phase change memory (PCM), resistive random access memory (RRAM), spin transfer torque (STT), spin-orbit torque (SOT), and DSHE, respectively.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1715-1722"},"PeriodicalIF":2.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Suppression of Drain-Bias-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs With Voltage Seatbelt 利用电压安全带抑制肖特基型 p-GaN 栅极 HEMT 中漏极偏压引发的 VTH 不稳定性

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3534168

Junting Chen;Haohao Chen;Yan Cheng;Jiongchong Fang;Zheng Wu;Junqiang Li;Jinjin Tang;Guosong Zeng;Kevin J. Chen;Mengyuan Hua

{"title":"Suppression of Drain-Bias-Induced VTH Instability in Schottky-Type p-GaN Gate HEMTs With Voltage Seatbelt","authors":"Junting Chen;Haohao Chen;Yan Cheng;Jiongchong Fang;Zheng Wu;Junqiang Li;Jinjin Tang;Guosong Zeng;Kevin J. Chen;Mengyuan Hua","doi":"10.1109/TED.2025.3534168","DOIUrl":"https://doi.org/10.1109/TED.2025.3534168","url":null,"abstract":"A cost-effective yet efficient approach is proposed for suppressing the drain-bias-induced threshold voltage (<inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula>) instability in Schottky-type p-gallium nitride (GaN) gate high electron mobility transistors (HEMTs). The proposed device consists of a source-connected metal layer on a dielectric layer in the gate-to-drain access region, which operates as a voltage seatbelt that restricts the voltage coupling to the p-GaN region from the drain within a defined range. By adjusting the dielectric thickness in the proposed structure, the voltage potential experienced by the p-GaN region is confined within a range of 3.1–22.3 V at a drain voltage (<inline-formula> <tex-math>${V} _{text {DS}}$ </tex-math></inline-formula>) of 400 V. In the scenario with a 3.1-V clamping voltage, the proposed configuration demonstrates a remarkable reduction of over 95% in <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> shift caused by the floating nature of p-GaN, along with a reduction of 88% in <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> shift induced by trapping effects. The proposed structure also enhances short-circuit robustness by reducing the saturation current density, while exerting only a minimal effect on the devices’ on-resistance (<inline-formula> <tex-math>${R} _{text {ON}}$ </tex-math></inline-formula>). The proposed structure offers room for balancing the tradeoff between the <inline-formula> <tex-math>${R} _{text {ON}}$ </tex-math></inline-formula> and the short-circuit robustness in practical applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1041-1046"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Neuromorphic Device With WOx/TiNOy Heterojunction for Airline Review Sentiment Prediction

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3537999

Fan Yang;Shixiong Liu;Cong Wang;Yang Li

引用次数: 0

Achieving 1-nm-Scale Equivalent Oxide Thickness Top-Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors With CMOS-Friendly Approaches

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2024.3466112

Jung-Soo Ko;Alexander B. Shearer;Sol Lee;Kathryn Neilson;Marc Jaikissoon;Kwanpyo Kim;Stacey F. Bent;Eric Pop;Krishna C. Saraswat

{"title":"Achieving 1-nm-Scale Equivalent Oxide Thickness Top-Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors With CMOS-Friendly Approaches","authors":"Jung-Soo Ko;Alexander B. Shearer;Sol Lee;Kathryn Neilson;Marc Jaikissoon;Kwanpyo Kim;Stacey F. Bent;Eric Pop;Krishna C. Saraswat","doi":"10.1109/TED.2024.3466112","DOIUrl":"https://doi.org/10.1109/TED.2024.3466112","url":null,"abstract":"Monolayer two-dimensional transition metal dichalcogenides (2-D TMDs) are promising semiconductors for future nanoscale transistors owing to their atomic thinness. However, atomic layer deposition (ALD) of gate dielectrics on 2-D TMDs has been difficult, and reducing the equivalent oxide thickness (EOT) with CMOS-compatible approaches remains a key challenge. Here, we report ultrathin top-gate dielectrics on monolayer TMDs using industry-friendly approaches, achieving 1-nm-scale top-gate EOT. We first show ALD of HfO2 on both monolayer WSe2 and MoS2 with a simple Si seed, enabling EOT <inline-formula> <tex-math>$approx ~0.9$ </tex-math></inline-formula> nm with subthreshold swing SS <inline-formula> <tex-math>$approx ~70$ </tex-math></inline-formula> mV/dec, low leakage, and negligible hysteresis on MoS2. We also demonstrate direct ALD of ultrathin alumina (AlOx) on monolayer MoS2 with good quality and uniformity using triethylaluminum (TEA) precursor, followed by ALD of HfO2. Combining our findings, we show that the threshold voltage (<inline-formula> <tex-math>${V}_{text {T}}$ </tex-math></inline-formula>) can be controlled by the interfacial dielectric layer on the 2-D transistor channel.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1514-1519"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143580905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effects of Homogeneous Buffer Layer on the Crystalline Quality and Electrical Properties of CdZnTe Epitaxial Films

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3531320

Xue Tian;Tingting Tan;Kun Cao;Xin Wan;Heming Wei;Ran Jiang;Yu Liu;Renying Cheng;Gangqiang Zha

{"title":"Effects of Homogeneous Buffer Layer on the Crystalline Quality and Electrical Properties of CdZnTe Epitaxial Films","authors":"Xue Tian;Tingting Tan;Kun Cao;Xin Wan;Heming Wei;Ran Jiang;Yu Liu;Renying Cheng;Gangqiang Zha","doi":"10.1109/TED.2025.3531320","DOIUrl":"https://doi.org/10.1109/TED.2025.3531320","url":null,"abstract":"The carrier transport process in CdZnTe epitaxial films is significantly influenced by the substantial lattice mismatch between the CdZnTe films and GaAs substrates. To mitigate this issue, a uniform buffer layer was fabricated between the substrates and the CdZnTe films using the close-space sublimation (CSS). The impact of the buffer layers on surface roughness and crystalline quality of the films was investigated through optical microscopy, atomic force microscopy, and X-ray diffraction. The effects on the electrical performance were studied through I–V tests and alpha-particle energy spectra. The results demonstrate that a uniform buffer layer, grown at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C for 5 min, significantly enhances the crystalline quality, resistivity, and carrier transport properties of the CdZnTe epitaxial films grown on low-resistance GaAs(001) substrates. After annealing at <inline-formula> <tex-math>$400~^{circ }$ </tex-math></inline-formula>C in a Te2 atmosphere for 4 h, the energy resolution of the detector improved to 1.5% in vacuum and 11.23% in air conditions.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1235-1241"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Influence of Surface Treatments on the Ohmic Contact Performance on the N-Face of Iron-Doped Semi-Insulating Freestanding GaN

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3534739

Yuanhang Sun;Yumin Zhang;Xiao Wang;Hao Zhou;Songyuan Xia;Qizhi Zhu;Wei Liu;Jianfeng Wang;Ke Xu

{"title":"Influence of Surface Treatments on the Ohmic Contact Performance on the N-Face of Iron-Doped Semi-Insulating Freestanding GaN","authors":"Yuanhang Sun;Yumin Zhang;Xiao Wang;Hao Zhou;Songyuan Xia;Qizhi Zhu;Wei Liu;Jianfeng Wang;Ke Xu","doi":"10.1109/TED.2025.3534739","DOIUrl":"https://doi.org/10.1109/TED.2025.3534739","url":null,"abstract":"To achieve superior electrical performance in vertical GaN-based devices on iron-doped semi-insulating gallium nitride (SI-GaN:Fe) substrates, a profound comprehension of the ohmic contact on the N-face of SI-GaN:Fe is imperative. The low carrier concentration and high bulk resistivity of SI-GaN:Fe, together with the complicated surface states of N-face, result in an excessively elevated specific contact resistance (<inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula>), posing a significant barrier to the realization of optimal ohmic contact. This study focuses on the surface treatments on the N-face of SI-GaN:Fe to reduce <inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula> of ohmic contact on it. Surface band bending (BB), surface roughness, and oxidation are all considered to investigate the influence of surface treatments on the ohmic contact performance on the N-face of SI-GaN:Fe. Among various treatments, samples subjected to inductively coupled plasma (ICP) dry etching followed by a wet etching in hydrochloric acid solution (HCl:H2O =1:2) demonstrated the most pronounced reduction in <inline-formula> <tex-math>$rho _{text {C}}$ </tex-math></inline-formula>. This is attributed to the surface BB after ICP etching, facilitating electron transition from the semiconductor to the metal. In addition, the N-face SI-GaN:Fe has a strong adsorption activity for oxygen, while the HCl solution effectively removes the surface GaOx layer and improves surface morphology, which is crucial for achieving ohmic contact. This study provides valuable insights into the fundamental physics of GaN ohmic contacts, thus enhancing the potential applicability of SI-GaN:Fe in vertical GaN-based devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1027-1034"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Sensitivity Analysis of Double Gate Dielectric-Modulated Thyristor for Highly Sensitive Biosensing

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3534172

Chan Heo;Jeongmin Son;M. Meyyappan;Kihyun Kim

{"title":"Design and Sensitivity Analysis of Double Gate Dielectric-Modulated Thyristor for Highly Sensitive Biosensing","authors":"Chan Heo;Jeongmin Son;M. Meyyappan;Kihyun Kim","doi":"10.1109/TED.2025.3534172","DOIUrl":"https://doi.org/10.1109/TED.2025.3534172","url":null,"abstract":"Biosensors with label-free and rapid detection capabilities have a critical impact on healthcare and environmental monitoring. Biosensors based on field-effect transistor (FET) are one of the most common and successful forms. They can detect the charged biomolecules, but it is impossible to detect the neutral biomolecules. Dielectric-modulated (DM) FETs overcome these limitations. However, as biosensor dimensions shrink to nanoscale for integration into mobile devices, such miniaturization leads to severe leakage current increase followed by standby power consumption, thereby creating a need to mitigate these issues. Thyristor devices have been studied recently in the memory and logic semiconductor fields as a promising candidate due to their low leakage current, high density, and fast operating speed. Taking advantage of these attributes, a thyristor-based DM biosensor with a nanocavity in the gate region to host the analytes is designed in this study and its biosensing characteristics are analyzed using technology computer-aided design (TCAD) simulations. The thyristor-based sensor shows high-voltage sensitivity exceeding 1, indicating its potential in future biosensing.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 3","pages":"1377-1382"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143521490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-Performance LLSAW Devices on X-Cut LiNbO₃ Thin Film With Bragg Reflector for n78 Band Applications

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3537587

Wei Fan;Dahao Wu;Zijie Wei;Peiran Li;Yuedong Wang;Zijiang Yang;Jingfu Bao;Yao Shuai;Bin Peng;Chuangui Wu;Ken-Ya Hashimoto;Wanli Zhang

{"title":"High-Performance LLSAW Devices on X-Cut LiNbO₃ Thin Film With Bragg Reflector for n78 Band Applications","authors":"Wei Fan;Dahao Wu;Zijie Wei;Peiran Li;Yuedong Wang;Zijiang Yang;Jingfu Bao;Yao Shuai;Bin Peng;Chuangui Wu;Ken-Ya Hashimoto;Wanli Zhang","doi":"10.1109/TED.2025.3537587","DOIUrl":"https://doi.org/10.1109/TED.2025.3537587","url":null,"abstract":"In this work, a range of high-performance longitudinal leaky surface acoustic wave (LLSAW) devices based on a composite substrate structure are designed and fabricated, specifically aimed at the 5G new radio (NR) n78 band. The substrate comprises an X-cut lithium niobate (LN) thin film and a Bragg reflector composed of alternating layers of SiO2 and Ta2O5. The fabricated LLSAW resonators exhibit exceptional performance with high admittance ratio (AR) and large electromechanical coupling coefficient (<inline-formula> <tex-math>$text {k}_{text {t}}^{{2}}$ </tex-math></inline-formula>) over a frequency range of 3.2–3.7 GHz. Specifically, a resonator centered at 3.317 GHz achieved an AR of 67 dB, a <inline-formula> <tex-math>$text {k}_{text {t}}^{{2}}$ </tex-math></inline-formula> of 20.4%, and a Bode-Qmax of 1219. Additionally, the fabricated filter with a center frequency of 3.4 GHz shows a minimum insertion loss (IL) of 1.35 dB, a 3-dB bandwidth of 433 MHz, and an attenuation of 43 dB in the n41 band. The filter also exhibits a low temperature coefficient of frequency (TCF) of −35.6/−40.2 ppm/°C. The filter demonstrates a 1-dB compression point (P1dB) of 15.2 dBm and an input third-order intercept point (IIP3) of 52.3 dBm, making it suitable for high-linearity, medium-power RF applications. These results demonstrate the potential of LLSAW technology based on X-cut LN thin film and SiO2/Ta2O5 reflectors for advanced 5G communication applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"1954-1960"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Novel Metal-Bridging Free Lift-Off Process for Fabricating High-Performance Sub-100-nm Gate Length MoS₂ Transistors

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3537064

Yun-Cheng Chang;Yuan-Chun Su;Hsiang-Chi Hu;Jian-Chen Tsai;Chih-Yao Shih;Chun-Jung Su;Pei-Wen Li;Wen-Hao Chang;Horng-Chih Lin

{"title":"A Novel Metal-Bridging Free Lift-Off Process for Fabricating High-Performance Sub-100-nm Gate Length MoS₂ Transistors","authors":"Yun-Cheng Chang;Yuan-Chun Su;Hsiang-Chi Hu;Jian-Chen Tsai;Chih-Yao Shih;Chun-Jung Su;Pei-Wen Li;Wen-Hao Chang;Horng-Chih Lin","doi":"10.1109/TED.2025.3537064","DOIUrl":"https://doi.org/10.1109/TED.2025.3537064","url":null,"abstract":"A novel approach for fabricating molybdenum disulfide (MoS2) transistors with sub-100-nm gate length is reported. Unlike the traditional lift-off process, the photoresist (PR) is not in contact with the MoS2 channel, while the metal deposited in the source/drain (S/D) areas is not bridged with that on PR through the PR sidewalls. A sacrificial oxide layer between the channel and the PR enables the two distinct features, which are done after generating the PR pattern that defines the S/D regions, selectively removing the sacrificial oxide to suspend the PR between the source and drain regions. When metal is subsequently deposited, the metal on the PR will naturally disconnect from that in the S/D regions due to the air gap between the PR and the channel. The new metal-bridging-free process frees the fabricated devices from many issues encountered in the traditional lift-off process. Besides, we combined the I-line photolithography and a novel PR trimming technique to demonstrate the feasibility of this approach in fabricating nanometer-scaled devices with high throughput. The fabricated MoS2 transistors with Au contacts exhibit S/D series resistance of 2.4 k<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula> m.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 4","pages":"2032-2037"},"PeriodicalIF":2.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143740428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thinking MOSFETs

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-02-10 DOI: 10.1109/TED.2025.3526127

Tom Jackson

引用次数: 0