IEEE Transactions on Electron Devices最新文献_第10页

A Photoelectric Synergistically Excited Cold-Cathode High-Frequency Radiation Source: From GHz to THz 一种光电协同激发冷阴极高频辐射源：从GHz到太赫兹

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3584747

Dong Han;Yan Shen;Zheyu Song;Pengbin Xu;Yanlin Ke;Shuai Tang;Yu Zhang;Huanjun Chen;Ningsheng Xu;Shaozhi Deng

{"title":"A Photoelectric Synergistically Excited Cold-Cathode High-Frequency Radiation Source: From GHz to THz","authors":"Dong Han;Yan Shen;Zheyu Song;Pengbin Xu;Yanlin Ke;Shuai Tang;Yu Zhang;Huanjun Chen;Ningsheng Xu;Shaozhi Deng","doi":"10.1109/TED.2025.3584747","DOIUrl":"https://doi.org/10.1109/TED.2025.3584747","url":null,"abstract":"High-frequency radiation source devices based on vacuum electronics hold significant application value in high-speed wireless communication and high-resolution radar imaging. Herein, we propose a photoelectric synergistic excitation of cold cathode for high-frequency radiation source device scheme, which can generate electromagnetic waves in the GHz-to-THz frequency range without the need for complex electron beam modulation components or additional microwave feed sources. In this study, based on a carbon nanotube (CNT) cold-cathode electron gun, we designed and successfully implemented a radiation source device capable of producing 12.2-GHz electromagnetic wave output under the coexcitation of picosecond laser pulses and a static electric field, achieving a peak output power of <inline-formula> <tex-math>$22.7~boldsymbol {mu } $ </tex-math></inline-formula>W. Based on the strategy, a radiation source device for 1 THz has been designed, which provides an option for the development of novel high-performance miniaturized terahertz radiation sources.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5163-5168"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K SiC衬底上具有钨栅极和高离子/ IOFF比的性能增强p沟道GaN MESFET工作在525 K

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3584327

Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang

{"title":"A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K","authors":"Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang","doi":"10.1109/TED.2025.3584327","DOIUrl":"https://doi.org/10.1109/TED.2025.3584327","url":null,"abstract":"In this letter, a normally-off p-channel GaN metal–semiconductor field-effect transistor (MESFET) on SiC substrate with high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio and barrier-freed ohmic contact was first demonstrated. Compared to the polarization-enhanced p-GaN/AlN/AlGaN on Si substrate, the same designed epitaxial wafer on SiC substrate showed a decreased surface potential from 11 to −368 mV as well as 1.9 times lower contact resistance (<inline-formula> <tex-math>${R}_{C}text {)}$ </tex-math></inline-formula>, modulated by dislocation-related potential. Meanwhile, high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$3.3times 10^{{7}}$ </tex-math></inline-formula>, ultralow hysteresis voltage of 0.05 V, and subthreshold swing (SS) of 83 mV/dec were obtained. The well-behaved characteristics of p-channel GaN MESFET on SiC substrate with negligible turn-on voltage and high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio show great potential for low-voltage complementary metal–oxide–semiconductor (CMOS) applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"4558-4562"},"PeriodicalIF":2.9,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localized GaN Cap Etching With Gate-Recessed Structure for Enhanced High-PAE Performance and Trap Analysis in 0.15- μ m AlGaN/GaN HEMTs 在0.15- μ m的AlGaN/GaN HEMTs中，栅极凹槽结构的局部GaN帽刻蚀提高了高pae性能和陷阱分析

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3586256

Beibei Lv;Siyuan Ma;Jiongjiong Mo

{"title":"Localized GaN Cap Etching With Gate-Recessed Structure for Enhanced High-PAE Performance and Trap Analysis in 0.15- μ m AlGaN/GaN HEMTs","authors":"Beibei Lv;Siyuan Ma;Jiongjiong Mo","doi":"10.1109/TED.2025.3586256","DOIUrl":"https://doi.org/10.1109/TED.2025.3586256","url":null,"abstract":"This article presents a comprehensive study on the impact of gate recessing strategies on the electrical performances and trap dynamics of 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) for high power-added efficiency (PAE) applications. By comparing devices with varying recess depths and their standard nonrecessed counterpart, we systematically investigate the trade-offs between device performance and process-induced damage. Device with GaN cap removal achieves a record output current density of 1393 mA/mm and a peak transconductance of 661 mS/mm, with reduced short-channel effects (SCEs) due to an increase in carrier concentration and a higher <inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${t}_{text {AlGaN}}$ </tex-math></inline-formula>. Notably, the gate-recessed device obtains an optimal recess depth with a PAE of 81.6% and Pout of 27.1 dBm at 10 GHz. Through stress measurement and RF transconductance analysis, we quantify the current collapse and the spatial distribution of border traps induced by inductively coupled plasma (ICP) etching. The results highlight that localized GaN cap removal offers a damage-mitigated pathway to enhance gate control, while excessive barrier thinning decreases the 2DEG concentration and exacerbates trap formation, leading to performance degradation. This work provides critical insights into optimizing gate-recessed designs for high-frequency power amplifiers by balancing structural benefits and process-induced defects.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4757-4763"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors 脉冲电压应力对无结铁电薄膜晶体管电退化影响的综合分析

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3586832

William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Ta-Chun Cho;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang

{"title":"Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors","authors":"William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Ta-Chun Cho;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang","doi":"10.1109/TED.2025.3586832","DOIUrl":"https://doi.org/10.1109/TED.2025.3586832","url":null,"abstract":"This work investigates the electrical degradation behavior of junctionless ferroelectric thin-film transistors (JL-FeTFTs) under various pulse voltage stress conditions, including pulsewidth (<inline-formula> <tex-math>${t} _{text {PW}}$ </tex-math></inline-formula>), pulse amplitude, and pulse polarity. The findings reveal that prolonged <inline-formula> <tex-math>${t} _{text {PW}}$ </tex-math></inline-formula> and higher pulse amplitude significantly degrade device performance, evidenced by increased subthreshold swing (SS), reduced transconductance (<inline-formula> <tex-math>${G} _{mathrm {m_max}}$ </tex-math></inline-formula>), and a decline in <sc>on</small>-state current. Furthermore, the pulse polarity plays a critical role, with bipolar pulse stress inducing more severe degradation than unipolar stress. Specifically, SS degradation and <inline-formula> <tex-math>${G} _{mathrm {m_max}}$ </tex-math></inline-formula> reduction under bipolar stress reach 0.331 V/decade and <inline-formula> <tex-math>$0.209times $ </tex-math></inline-formula>, respectively, compared to 0.055 V/decade and <inline-formula> <tex-math>$0.779times $ </tex-math></inline-formula> for positive unipolar stress. The results suggest that the additional damage caused by polarity switching is attributed to the intensified electric field stress during ferroelectric polarization reversal. Under negative unipolar pulse stress, a pronounced <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> reduction due to hole trapping overshadows SS degradation, whereas positive unipolar stress primarily increases <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> with minimal charge trapping effects. These findings provide valuable insights into the reliability of JL-FeTFTs in memory operations, guiding the selection of optimal pulse conditions for memory write and erase processes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4865-4871"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Full-Bridge Vortex-Type Tunneling Magnetoresistive Sensor on a Single Die 单模全桥涡隧道磁阻传感器

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3579462

Wei Su;Jiaming Liu;Xianfeng Liang;Mengmeng Guan;Jieqiang Gao;Haifeng Gao;Zhiguang Wang;Jinghong Guo;Zhongqiang Hu;Ming Liu

引用次数: 0

Effects of Passivation Layers on the Characteristics and Stability of Indium–Gallium–Zinc Oxide Thin-Film Transistors 钝化层对铟镓锌氧化物薄膜晶体管特性和稳定性的影响

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3582235

Yuzhen Zhang;Qiuxiao Feng;Wangran Wu;Runxiao Shi;Weifeng Sun;Man Wong

引用次数: 0

Ga2O3 Vertical SBD With Suspended Field Plate-Assisted Shallow Mesa Termination for Multikilovolt and Ampere-Class Applications 用于多千伏和安培级应用的Ga2O3垂直SBD，具有悬浮场板辅助浅台面终端

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-10 DOI: 10.1109/TED.2025.3584011

Xueli Han;Xiaorui Xu;Zhengbo Wang;Hanchao Yang;Desen Chen;Yicong Deng;Duanyang Chen;Haizhong Zhang;Hongji Qi

{"title":"Ga2O3 Vertical SBD With Suspended Field Plate-Assisted Shallow Mesa Termination for Multikilovolt and Ampere-Class Applications","authors":"Xueli Han;Xiaorui Xu;Zhengbo Wang;Hanchao Yang;Desen Chen;Yicong Deng;Duanyang Chen;Haizhong Zhang;Hongji Qi","doi":"10.1109/TED.2025.3584011","DOIUrl":"https://doi.org/10.1109/TED.2025.3584011","url":null,"abstract":"In this work, a vertical gallium oxide (Ga2O3) Schottky barrier diode (SBD) with suspended field plate-assisted shallow mesa termination (SFPM-SBD) is proposed and fabricated. The suspended field plate is achieved by using Cl2 in the ICP etching process to facilitate isotropic etching of Ga2O3. Compared with shallow mesa SBD, the introduction of SFPM can further optimize the electric field (E_Field) distribution. Consequently, a high breakdown voltage (BV) of over 3.5 kV and a low specific <sc>on</small>-resistance of 5.77 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2 are achieved, resulting in a power figure of merit (PFOM) >2.12 GW/cm2. Furthermore, the large-area device with <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> mm2 is fabricated, achieving a BV exceeding 1.5 kV and a high forward current of 12 A at 2 V. The simplified fabrication process of the SFPM-SBD, combined with its outstanding performance, makes it a promising candidate for multikilovolt and ampere-class applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"4307-4312"},"PeriodicalIF":2.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Performance Trade-Off in Ultrathin Channel IGZTO TFTs 超薄通道IGZTO TFTs的电气性能权衡

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-10 DOI: 10.1109/TED.2025.3585479

Kai Chen;Ran Cheng;Rui Zhang;Junkang Li;Yunlong Li

{"title":"Electrical Performance Trade-Off in Ultrathin Channel IGZTO TFTs","authors":"Kai Chen;Ran Cheng;Rui Zhang;Junkang Li;Yunlong Li","doi":"10.1109/TED.2025.3585479","DOIUrl":"https://doi.org/10.1109/TED.2025.3585479","url":null,"abstract":"The scaling of channel thickness (<inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula>) in thin-film transistors (TFTs) is critical for optimizing device performance for advanced electronic applications. In this study, the performance of ultrathin channel indium–gallium–zinc–tin-oxide (IGZTO) TFTs ranging from 3 to 10 nm has been systematically investigated, focusing on the trade-off between <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula> and device performance. As <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula> decreases, the energy bandgap of IGZTO films broadens, leading to an increased conduction band-to-Fermi level energy difference. This results in a higher threshold voltage (<inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula>) and reduced mobility. For channels thinner than 4.5 nm, the impact of surface roughness scattering and bulk traps becomes more pronounced, causing the degradation of hysteresis and positive bias temperature instability (PBTI). In contrast, thicker IGZTO channels exhibit enhanced metal–oxygen (M–O) bonding, improving PBTI reliability. The optimal balance between performance and PBTI is achieved in devices with a 4.5-nm-thick IGZTO channel, demonstrating a mobility of 32.5 cm2 (V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>s)<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>, a <inline-formula> <tex-math>${V} _{text {th}}$ </tex-math></inline-formula> of 0.6 V, minimal hysteresis of 23.9 mV, and a subthreshold swing (SS) of 78 mV<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>dec<inline-formula> <tex-math>${}^{-{1}}$ </tex-math></inline-formula>. These results highlight the importance of balancing <inline-formula> <tex-math>${T} _{text {CH}}$ </tex-math></inline-formula>, performance, and PBTI to optimize IGZTO TFTs with ultrathin channels for low-power, high-performance applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4941-4947"},"PeriodicalIF":3.2,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and Optimization of ESD Protection Structure Triggered by Polysilicon Diode for Low- and Medium-Voltage ICs 中低压集成电路中多晶硅二极管触发ESD保护结构的设计与优化

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-10 DOI: 10.1109/TED.2025.3586228

Hailian Liang;Jian Xu;Junliang Liu;Jianfeng Li;Haoran Jin;Chen Luo;ChaoJin Zhang

{"title":"Design and Optimization of ESD Protection Structure Triggered by Polysilicon Diode for Low- and Medium-Voltage ICs","authors":"Hailian Liang;Jian Xu;Junliang Liu;Jianfeng Li;Haoran Jin;Chen Luo;ChaoJin Zhang","doi":"10.1109/TED.2025.3586228","DOIUrl":"https://doi.org/10.1109/TED.2025.3586228","url":null,"abstract":"A novel silicon-controlled rectifier (SCR) triggered by multiple polysilicon diodes (MPDTSCR) is proposed and investigated for electrostatic discharge (ESD) protection in low- and medium-voltage integrated circuits (ICs). Typically, the turn-on voltage of a conventional diode-triggered SCR (DTSCR) does not increase linearly when more than three diodes in series, due to parasitic effects caused by the complex bipolar transistors formed by multiple p-n junctions, leading to unpredictable turn-on voltage and increased leakage current. By innovatively designing a compact polysilicon-diode triggering circuit, the MPDTSCR with six polysilicon diodes exhibits excellent anti-parasitic ability and favorable electrical characteristics, achieving a low breakdown voltage of 4.2 V, a small leakage current in the nanoampere scales, and high robustness with a failure current level of 6.6 A per finger. By minimizing the space between the p- and n-type regions of the polysilicon, the turn-on voltage of the MPDTSCR is reduced from 17.2 to 13 V, without degrading the ESD robustness. Therefore, the SCR embedded with a compact polysilicon-diode-triggering circuit effectively suppresses parasitic effects. The MPDTSCR, with its innovative design and adjustable number of polysilicon diodes, offers excellent adaptability for effective ESD protection in low- and medium-voltage applications, ensuring comprehensive protection and highlighting its significance in enhancing the reliability and stability of modern electronic systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4629-4634"},"PeriodicalIF":3.2,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power, Performance, and Area Analysis of Ultra-Stacked Forksheet-FET for Angstrom Nodes 超堆叠叉片场效应晶体管的功率、性能和面积分析

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-10 DOI: 10.1109/TED.2025.3582225

Junjong Lee;Sanguk Lee;Yonghwan Ahn;Minchan Kim;Gunryeol Cho;Sunmin Yeou;Sung-Kyu Lim;Rock-Hyun Baek

{"title":"Power, Performance, and Area Analysis of Ultra-Stacked Forksheet-FET for Angstrom Nodes","authors":"Junjong Lee;Sanguk Lee;Yonghwan Ahn;Minchan Kim;Gunryeol Cho;Sunmin Yeou;Sung-Kyu Lim;Rock-Hyun Baek","doi":"10.1109/TED.2025.3582225","DOIUrl":"https://doi.org/10.1109/TED.2025.3582225","url":null,"abstract":"For the first time, this study investigated the standard cell and chip-level power, performance, and area (PPA) benefit of ultra-stacked forksheet-FET (FSFET) with five channels for Angstrom nodes. Five-stack FSFET shows a smaller channel width than conventional four-stack FSFET at the same drive current condition, enabling additional scaling. In conventional nanosheet-FET (NSFET), a large number of channels increases parasitic resistance and capacitance, which degrades device performance. However, the wall of FSFET, the wrap-around contact, the metal source/drain, and the small vertical spacing of the channel can mitigate the increases in parasitics. Therefore, a five-stack FSFET can achieve a small footprint without frequency degradation. We developed 4T standard cells with heights of 76 and 68 nm for four-stack FSFET and five-stack FSFET, respectively. In the same device performance condition, the five-stack FSFET-based cells show a smaller energy-delay product due to the small capacitance. Five-stack FSFET-based chip shows a 10.5%~10.7% smaller area and 7.0%~7.5% shorter wire length for all benchmarks. The shorter wire length reduces wire capacitance; thus, the five-stack FSFET-based chip shows a smaller power consumption. On the other hand, the five-stack FSFET has a smaller metal width and a larger wire resistance. However, the five-stack FSFET-based chip shows only a slight increase in power-delay product (PDP) due to the gate-dominated circuit, great optimization using buffer insertion, and a backside power delivery network (BS-PDN). Overall, the five-stack FSFET-based chip shows only a slightly degraded PDP with 10.5%~10.7% smaller area. Ultra-stacked FSFET enables additional scaling, with only an increase in channel number before adopting complementary-FET (CFET).","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"3966-3973"},"PeriodicalIF":2.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0