IEEE Transactions on Electron Devices最新文献_第10页

Improved Stability of Fully Recessed Normally-Off GaN MIS-HEMTs With SiNx/AlN Dielectric Stack 具有SiNx/AlN介电层的全凹槽正常关断GaN mishemt的稳定性提高

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-14 DOI: 10.1109/TED.2025.3585908

Yu Li;Guohao Yu;Ang Li;Haochen Zhang;An Yang;Yingfei Sun;Bohan Guo;Huixin Yue;Chunfeng Hao;Shaoqian Lu;Bosen Liu;Xuguang Deng;Yong Cai;Zhongming Zeng;Baoshun Zhang

{"title":"Improved Stability of Fully Recessed Normally-Off GaN MIS-HEMTs With SiNx/AlN Dielectric Stack","authors":"Yu Li;Guohao Yu;Ang Li;Haochen Zhang;An Yang;Yingfei Sun;Bohan Guo;Huixin Yue;Chunfeng Hao;Shaoqian Lu;Bosen Liu;Xuguang Deng;Yong Cai;Zhongming Zeng;Baoshun Zhang","doi":"10.1109/TED.2025.3585908","DOIUrl":"https://doi.org/10.1109/TED.2025.3585908","url":null,"abstract":"This work presents a comparative study of GaN metal-insulator-semiconductor high-electron-mobility-transistors (MIS-HEMTs) employing LPCVD-SiNx/ALD-AlN or PEALD-SiO2/ALD-AlN dielectric stacks. The SiNx/AlN MIS-HEMTs exhibit a minimal threshold voltage shift (<inline-formula> <tex-math>$Delta {V}_{text {TH}}$ </tex-math></inline-formula>) of −0.24 V with an on/off current ratio up to <inline-formula> <tex-math>$10^{{8}}$ </tex-math></inline-formula> under <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C, compared to <inline-formula> <tex-math>$Delta {V}_{text {TH}}=2.0$ </tex-math></inline-formula> V for SiO2/AlN MIS-HEMTs. Under gate bias stress, SiNx/AlN devices show <inline-formula> <tex-math>$Delta {V}_{text {TH}}$ </tex-math></inline-formula> of −0.90 V (positive) and −0.45 V (negative), versus −1.75 and 3.31 V for SiO2/AlN devices. After maintaining <inline-formula> <tex-math>$10^{{4}}$ </tex-math></inline-formula> s of off-state drain-bias stress, SiNx/AlN MIS-HEMT achieves a small <inline-formula> <tex-math>$Delta {V}_{text {TH}}$ </tex-math></inline-formula> of −0.45 V. The improved stability is attributed to the better interface quality of SiNx/AlN stack, enabled by the low-pressure chemical vapor deposition (LPCVD) process and nitrogen-rich environment. These findings underscore the potential of LPCVD-SiNx/ALD-AlN dielectric stacks in advancing GaN MIS-HEMTs for high-performance and reliable power switching applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4764-4769"},"PeriodicalIF":3.2,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of Nanoscale Bonding-Based Complementary FETs 纳米级键合互补场效应管的研究

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-14 DOI: 10.1109/TED.2025.3585900

Seung Kyu Kim;Johyeon Kim;Kee-Won Kwon;Jongwook Jeon

{"title":"Investigation of Nanoscale Bonding-Based Complementary FETs","authors":"Seung Kyu Kim;Johyeon Kim;Kee-Won Kwon;Jongwook Jeon","doi":"10.1109/TED.2025.3585900","DOIUrl":"https://doi.org/10.1109/TED.2025.3585900","url":null,"abstract":"In this article, the nanoscale bonding-based complementary field-effect transistor (B-CFET) is proposed as a high-performance alternative to sequential CFETs (S-CFETs) for next-generation technology nodes. Unlike S-CFETs, which suffer from thermal budget constraints that lead to junction abruptness degradation, B-CFET mitigates these issues by employing low-temperature bonding techniques for CFET integration. This approach enables the use of heterogeneous channel materials and allows independent nMOS/pMOS optimization. To assess its performance feasibility, B-CFET is compared with S-CFET. 3-D TCAD simulations indicate that, when accounting for the junction abruptness degradation of S-CFET’s bottom transistor due to dopant diffusion (assuming an increase of 1 nm per decade), B-CFET achieves an 11.1% improvement in operating frequency at the same leakage power (<inline-formula> <tex-math>${f}_{text {ISOLEAK}}text {)}$ </tex-math></inline-formula> compared to S-CFET. Although additional bonding bump layers extend vertical interconnects or cause misalignment and void formation, potentially increasing external resistance, segmented resistance analysis indicates that these factors have a negligible impact on overall performance. Even under extreme conditions, where the bonding resistance increases significantly from 17.5 to <inline-formula> <tex-math>$60.7~Omega $ </tex-math></inline-formula> (a 247% increase), B-CFET exhibits excellent robustness, with only a 1.0% degradation in <inline-formula> <tex-math>${f}_{text {ISOLEAK}}$ </tex-math></inline-formula>. This minimal degradation highlights the negligible influence of (<inline-formula> <tex-math>${R}_{text {BUMP}}text {)}$ </tex-math></inline-formula> on overall performance and reinforces its potential as a scalable and resilient architecture for future CFET technologies.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4614-4620"},"PeriodicalIF":3.2,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Physical Modeling of Photonic Characteristics in Amorphous Oxide TFTs Incorporating Trap State Excitation and Carrier Percolation 包含陷阱态激发和载流子渗透的非晶氧化物tft光子特性的物理建模

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-14 DOI: 10.1109/TED.2025.3586833

Bo Yan;Lei Zhou;Rui-Peng Chen;Miao Xu;Lei Wang;Wei-Jing Wu;Jun-Biao Peng

引用次数: 0

A Photoelectric Synergistically Excited Cold-Cathode High-Frequency Radiation Source: From GHz to THz 一种光电协同激发冷阴极高频辐射源：从GHz到太赫兹

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3584747

Dong Han;Yan Shen;Zheyu Song;Pengbin Xu;Yanlin Ke;Shuai Tang;Yu Zhang;Huanjun Chen;Ningsheng Xu;Shaozhi Deng

{"title":"A Photoelectric Synergistically Excited Cold-Cathode High-Frequency Radiation Source: From GHz to THz","authors":"Dong Han;Yan Shen;Zheyu Song;Pengbin Xu;Yanlin Ke;Shuai Tang;Yu Zhang;Huanjun Chen;Ningsheng Xu;Shaozhi Deng","doi":"10.1109/TED.2025.3584747","DOIUrl":"https://doi.org/10.1109/TED.2025.3584747","url":null,"abstract":"High-frequency radiation source devices based on vacuum electronics hold significant application value in high-speed wireless communication and high-resolution radar imaging. Herein, we propose a photoelectric synergistic excitation of cold cathode for high-frequency radiation source device scheme, which can generate electromagnetic waves in the GHz-to-THz frequency range without the need for complex electron beam modulation components or additional microwave feed sources. In this study, based on a carbon nanotube (CNT) cold-cathode electron gun, we designed and successfully implemented a radiation source device capable of producing 12.2-GHz electromagnetic wave output under the coexcitation of picosecond laser pulses and a static electric field, achieving a peak output power of <inline-formula> <tex-math>$22.7~boldsymbol {mu } $ </tex-math></inline-formula>W. Based on the strategy, a radiation source device for 1 THz has been designed, which provides an option for the development of novel high-performance miniaturized terahertz radiation sources.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"5163-5168"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K SiC衬底上具有钨栅极和高离子/ IOFF比的性能增强p沟道GaN MESFET工作在525 K

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3584327

Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang

{"title":"A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K","authors":"Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang","doi":"10.1109/TED.2025.3584327","DOIUrl":"https://doi.org/10.1109/TED.2025.3584327","url":null,"abstract":"In this letter, a normally-off p-channel GaN metal–semiconductor field-effect transistor (MESFET) on SiC substrate with high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio and barrier-freed ohmic contact was first demonstrated. Compared to the polarization-enhanced p-GaN/AlN/AlGaN on Si substrate, the same designed epitaxial wafer on SiC substrate showed a decreased surface potential from 11 to −368 mV as well as 1.9 times lower contact resistance (<inline-formula> <tex-math>${R}_{C}text {)}$ </tex-math></inline-formula>, modulated by dislocation-related potential. Meanwhile, high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$3.3times 10^{{7}}$ </tex-math></inline-formula>, ultralow hysteresis voltage of 0.05 V, and subthreshold swing (SS) of 83 mV/dec were obtained. The well-behaved characteristics of p-channel GaN MESFET on SiC substrate with negligible turn-on voltage and high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio show great potential for low-voltage complementary metal–oxide–semiconductor (CMOS) applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"4558-4562"},"PeriodicalIF":2.9,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Localized GaN Cap Etching With Gate-Recessed Structure for Enhanced High-PAE Performance and Trap Analysis in 0.15- μ m AlGaN/GaN HEMTs 在0.15- μ m的AlGaN/GaN HEMTs中，栅极凹槽结构的局部GaN帽刻蚀提高了高pae性能和陷阱分析

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3586256

Beibei Lv;Siyuan Ma;Jiongjiong Mo

{"title":"Localized GaN Cap Etching With Gate-Recessed Structure for Enhanced High-PAE Performance and Trap Analysis in 0.15- μ m AlGaN/GaN HEMTs","authors":"Beibei Lv;Siyuan Ma;Jiongjiong Mo","doi":"10.1109/TED.2025.3586256","DOIUrl":"https://doi.org/10.1109/TED.2025.3586256","url":null,"abstract":"This article presents a comprehensive study on the impact of gate recessing strategies on the electrical performances and trap dynamics of 0.15-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m aluminum gallium nitride (AlGaN)/gallium nitride (GaN) high-electron-mobility transistors (HEMTs) for high power-added efficiency (PAE) applications. By comparing devices with varying recess depths and their standard nonrecessed counterpart, we systematically investigate the trade-offs between device performance and process-induced damage. Device with GaN cap removal achieves a record output current density of 1393 mA/mm and a peak transconductance of 661 mS/mm, with reduced short-channel effects (SCEs) due to an increase in carrier concentration and a higher <inline-formula> <tex-math>${L}_{text {g}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${t}_{text {AlGaN}}$ </tex-math></inline-formula>. Notably, the gate-recessed device obtains an optimal recess depth with a PAE of 81.6% and Pout of 27.1 dBm at 10 GHz. Through stress measurement and RF transconductance analysis, we quantify the current collapse and the spatial distribution of border traps induced by inductively coupled plasma (ICP) etching. The results highlight that localized GaN cap removal offers a damage-mitigated pathway to enhance gate control, while excessive barrier thinning decreases the 2DEG concentration and exacerbates trap formation, leading to performance degradation. This work provides critical insights into optimizing gate-recessed designs for high-frequency power amplifiers by balancing structural benefits and process-induced defects.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4757-4763"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144904885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors 脉冲电压应力对无结铁电薄膜晶体管电退化影响的综合分析

IF 3.2 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3586832

William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Ta-Chun Cho;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang

{"title":"Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors","authors":"William Cheng-Yu Ma;Chun-Jung Su;Kuo-Hsing Kao;Ta-Chun Cho;Yu-Chieh Yen;Ji-Min Yang;Yi-Han Li;Yen-Chen Chen;Jhe-Yu Lin;Hui-Wen Chang","doi":"10.1109/TED.2025.3586832","DOIUrl":"https://doi.org/10.1109/TED.2025.3586832","url":null,"abstract":"This work investigates the electrical degradation behavior of junctionless ferroelectric thin-film transistors (JL-FeTFTs) under various pulse voltage stress conditions, including pulsewidth (<inline-formula> <tex-math>${t} _{text {PW}}$ </tex-math></inline-formula>), pulse amplitude, and pulse polarity. The findings reveal that prolonged <inline-formula> <tex-math>${t} _{text {PW}}$ </tex-math></inline-formula> and higher pulse amplitude significantly degrade device performance, evidenced by increased subthreshold swing (SS), reduced transconductance (<inline-formula> <tex-math>${G} _{mathrm {m_max}}$ </tex-math></inline-formula>), and a decline in <sc>on</small>-state current. Furthermore, the pulse polarity plays a critical role, with bipolar pulse stress inducing more severe degradation than unipolar stress. Specifically, SS degradation and <inline-formula> <tex-math>${G} _{mathrm {m_max}}$ </tex-math></inline-formula> reduction under bipolar stress reach 0.331 V/decade and <inline-formula> <tex-math>$0.209times $ </tex-math></inline-formula>, respectively, compared to 0.055 V/decade and <inline-formula> <tex-math>$0.779times $ </tex-math></inline-formula> for positive unipolar stress. The results suggest that the additional damage caused by polarity switching is attributed to the intensified electric field stress during ferroelectric polarization reversal. Under negative unipolar pulse stress, a pronounced <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> reduction due to hole trapping overshadows SS degradation, whereas positive unipolar stress primarily increases <inline-formula> <tex-math>${V} _{text {TH}}$ </tex-math></inline-formula> with minimal charge trapping effects. These findings provide valuable insights into the reliability of JL-FeTFTs in memory operations, guiding the selection of optimal pulse conditions for memory write and erase processes.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 9","pages":"4865-4871"},"PeriodicalIF":3.2,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144909373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Full-Bridge Vortex-Type Tunneling Magnetoresistive Sensor on a Single Die 单模全桥涡隧道磁阻传感器

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3579462

Wei Su;Jiaming Liu;Xianfeng Liang;Mengmeng Guan;Jieqiang Gao;Haifeng Gao;Zhiguang Wang;Jinghong Guo;Zhongqiang Hu;Ming Liu

引用次数: 0

Effects of Passivation Layers on the Characteristics and Stability of Indium–Gallium–Zinc Oxide Thin-Film Transistors 钝化层对铟镓锌氧化物薄膜晶体管特性和稳定性的影响

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3582235

Yuzhen Zhang;Qiuxiao Feng;Wangran Wu;Runxiao Shi;Weifeng Sun;Man Wong

引用次数: 0

Ga2O3 Vertical SBD With Suspended Field Plate-Assisted Shallow Mesa Termination for Multikilovolt and Ampere-Class Applications 用于多千伏和安培级应用的Ga2O3垂直SBD，具有悬浮场板辅助浅台面终端

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-10 DOI: 10.1109/TED.2025.3584011

Xueli Han;Xiaorui Xu;Zhengbo Wang;Hanchao Yang;Desen Chen;Yicong Deng;Duanyang Chen;Haizhong Zhang;Hongji Qi

{"title":"Ga2O3 Vertical SBD With Suspended Field Plate-Assisted Shallow Mesa Termination for Multikilovolt and Ampere-Class Applications","authors":"Xueli Han;Xiaorui Xu;Zhengbo Wang;Hanchao Yang;Desen Chen;Yicong Deng;Duanyang Chen;Haizhong Zhang;Hongji Qi","doi":"10.1109/TED.2025.3584011","DOIUrl":"https://doi.org/10.1109/TED.2025.3584011","url":null,"abstract":"In this work, a vertical gallium oxide (Ga2O3) Schottky barrier diode (SBD) with suspended field plate-assisted shallow mesa termination (SFPM-SBD) is proposed and fabricated. The suspended field plate is achieved by using Cl2 in the ICP etching process to facilitate isotropic etching of Ga2O3. Compared with shallow mesa SBD, the introduction of SFPM can further optimize the electric field (E_Field) distribution. Consequently, a high breakdown voltage (BV) of over 3.5 kV and a low specific <sc>on</small>-resistance of 5.77 m<inline-formula> <tex-math>$Omega cdot $ </tex-math></inline-formula>cm2 are achieved, resulting in a power figure of merit (PFOM) >2.12 GW/cm2. Furthermore, the large-area device with <inline-formula> <tex-math>$3times 3$ </tex-math></inline-formula> mm2 is fabricated, achieving a BV exceeding 1.5 kV and a high forward current of 12 A at 2 V. The simplified fabrication process of the SFPM-SBD, combined with its outstanding performance, makes it a promising candidate for multikilovolt and ampere-class applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"4307-4312"},"PeriodicalIF":2.9,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0