Comprehensive Analysis of Pulse Voltage Stress Effects on Electrical Degradation in Junctionless Ferroelectric Thin-Film Transistors

Abstract

This work investigates the electrical degradation behavior of junctionless ferroelectric thin-film transistors (JL-FeTFTs) under various pulse voltage stress conditions, including pulsewidth ( ${t} _{\text {PW}}$ ), pulse amplitude, and pulse polarity. The findings reveal that prolonged ${t} _{\text {PW}}$ and higher pulse amplitude significantly degrade device performance, evidenced by increased subthreshold swing (SS), reduced transconductance ( ${G} _{\mathrm {m\_max}}$ ), and a decline in on-state current. Furthermore, the pulse polarity plays a critical role, with bipolar pulse stress inducing more severe degradation than unipolar stress. Specifically, SS degradation and ${G} _{\mathrm {m\_max}}$ reduction under bipolar stress reach 0.331 V/decade and $0.209\times $ , respectively, compared to 0.055 V/decade and $0.779\times $ for positive unipolar stress. The results suggest that the additional damage caused by polarity switching is attributed to the intensified electric field stress during ferroelectric polarization reversal. Under negative unipolar pulse stress, a pronounced ${V} _{\text {TH}}$ reduction due to hole trapping overshadows SS degradation, whereas positive unipolar stress primarily increases ${V} _{\text {TH}}$ with minimal charge trapping effects. These findings provide valuable insights into the reliability of JL-FeTFTs in memory operations, guiding the selection of optimal pulse conditions for memory write and erase processes.