IEEE Transactions on Electron Devices最新文献

Compact Model of Enhancement-Mode GaN HEMTs Realized by Charge-Trap Layer Structure 电荷阱层结构实现增强模式GaN hemt的紧凑模型

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-08 DOI: 10.1109/TED.2026.3707823

Kang Hee Lee;Junseok Heo;Hyunwoo Kim;Jang Hyun Kim

{"title":"Compact Model of Enhancement-Mode GaN HEMTs Realized by Charge-Trap Layer Structure","authors":"Kang Hee Lee;Junseok Heo;Hyunwoo Kim;Jang Hyun Kim","doi":"10.1109/TED.2026.3707823","DOIUrl":"https://doi.org/10.1109/TED.2026.3707823","url":null,"abstract":"With the advancement of gallium nitride (GaN) high electron mobility transistor (HEMT) technology, various compact models have been investigated, with an advanced SPICE model for HEMT (ASM-HEMT) and the MIT virtual source GaN (MVSG) established as industry standards. While compact modeling for p-GaN gate devices for enhancement-mode (E-mode) implementation has been extensively researched. However, models for emerging E-mode devices utilizing charge-trap layers (CTLs) or ferroelectrics remain underexplored. This article proposes a compact model for a CTL-based E-mode GaN HEMT. To ensure physical reliability, the proposed model adopts the standard MVSG model as its core framework. It accurately describes the program operation, where channel electrons are trapped in the CTL through tunneling, and the retention characteristics, where trapped charges are detrapped over time. By capturing complex physical mechanisms through efficient fitting parameters, the model demonstrates high agreement with measurement data from fabricated devices. The model was implemented in Verilog-A and verified through HSPICE simulations, proving its compatibility and utility for circuit design applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5318-5326"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Back-Gate Effect Mechanism and Mitigation in High-Voltage Thick-Layer SOI pLDMOS Using a Field Plate-Bulk Dual Depletion Structure 采用场极板-体双损耗结构的高压厚层SOI pLDMOS的后门效应机理及抑制

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-27 DOI: 10.1109/TED.2026.3714753

Ying Xiang;Teng Liu;Nailong He;Yujing Fu;Jingchuan Zhao;Zhenyan Liu;Dingxiang Ma;Zhili Zhang;Lin Bai;Liqi An;Yongshun Li;Liang Song;Huajun Jin;Sen Zhang;Wentong Zhang;Bo Zhang

{"title":"Back-Gate Effect Mechanism and Mitigation in High-Voltage Thick-Layer SOI pLDMOS Using a Field Plate-Bulk Dual Depletion Structure","authors":"Ying Xiang;Teng Liu;Nailong He;Yujing Fu;Jingchuan Zhao;Zhenyan Liu;Dingxiang Ma;Zhili Zhang;Lin Bai;Liqi An;Yongshun Li;Liang Song;Huajun Jin;Sen Zhang;Wentong Zhang;Bo Zhang","doi":"10.1109/TED.2026.3714753","DOIUrl":"https://doi.org/10.1109/TED.2026.3714753","url":null,"abstract":"The impact of the back-gate effect on the breakdown voltage (BV) of high-voltage thick-layer p-channel laterally diffused MOSFET (pLDMOS) is investigated, and the design challenge of achieving low specific <sc>on</small>-resistance (<inline-formula> <tex-math>${R} _{text {on,sp}}$ </tex-math></inline-formula>) posed by the back-gate effect is analyzed. A novel pLDMOS featuring a field plate-bulk dual depletion (FP-BD) structure is proposed. By implementing a graded doping profile in the drift region to form a buried N-bulk layer, the structure enables dual depletion between the bulk layer and the surface field plate. This produces a quasi-RESURF electric field distribution, transforming the surface electric field from a single-peak to a double-peak profile. Experimental results show that as the back-gate-to-source voltage sweeps from 0 to −200 V, the BV of the proposed FP-BD pLDMOS decreases by only 12.0%, compared to a 48.2% drop in the conventional device. Furthermore, the structure achieves an extremely low <inline-formula> <tex-math>${R} _{text {on,sp}}$ </tex-math></inline-formula> of 21.04 m<inline-formula> <tex-math>$Omega {cdot }text {cm}^{2}$ </tex-math></inline-formula> at a BV of 283.1 V, representing a 57.8% reduction relative to the RESURF condition. Highly compatible with standard process platforms, this FP-BD structure provides an effective performance-optimization solution for high-voltage thick-layer SOI devices.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5466-5470"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive Investigation on Degradation of SiC SBD-Embedded MOSFET Under Repetitive UIS Stress SiC sbd嵌入式MOSFET在重复应力作用下的退化综合研究

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-31 DOI: 10.1109/TED.2026.3715459

Ziwei Hu;Jiafei Yao;Fan Yang;Yuxuan Dai;Zijing Yue;Jie Long;Jing Chen;Jing Wang;Man Li;Kemeng Yang;Zhikuang Cai;Yufeng Guo

{"title":"Comprehensive Investigation on Degradation of SiC SBD-Embedded MOSFET Under Repetitive UIS Stress","authors":"Ziwei Hu;Jiafei Yao;Fan Yang;Yuxuan Dai;Zijing Yue;Jie Long;Jing Chen;Jing Wang;Man Li;Kemeng Yang;Zhikuang Cai;Yufeng Guo","doi":"10.1109/TED.2026.3715459","DOIUrl":"https://doi.org/10.1109/TED.2026.3715459","url":null,"abstract":"This article investigates the degradation mechanisms of 1.2-kV silicon carbide (SiC) MOSFETs with an embedded Schottky barrier diode (SBD) under repetitive unclamped inductive switching (UIS) stress, in comparison with SiC conventional planar MOSFETs. TCAD simulation results show that repetitive UIS stress induces a high impact ionization rate and strong electric field in the JFET region of both devices, resulting in hot hole injection into the gate oxide above the JFET region, as corroborated by <inline-formula> <tex-math>$C$ </tex-math></inline-formula>–<inline-formula> <tex-math>$V$ </tex-math></inline-formula> characteristics. However, for the SBD-embedded device, a higher SiO2/SiC interface trap density additionally promotes hole trapping in the gate oxide above the channel region, leading to a pronounced negative threshold voltage (<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula>) shift of 9.5%. Both devices also exhibit a significant increase in <sc>on</small>-state resistance (<inline-formula> <tex-math>${R}_{text{on}}$ </tex-math></inline-formula>), which is primarily attributed to thermomechanical stress induced by the coefficient of thermal expansion (CTE) mismatch, causing source metal reconstruction in the SBD-embedded device and bonding wire lift-off and warping in the conventional device, accompanied by bipolar degradation in the drift region. After 50 K repetitive UIS stress cycles, Schottky metal degradation is observed in the SBD-embedded device, whereas gate oxide breakdown occurs in the conventional device. Finally, the single-pulse avalanche capability of the SBD-embedded device is severely limited by an SBD-induced positive feedback loop between the lattice temperature and the SBD leakage current.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5484-5492"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Trap-Induced Dynamic Degradation in AlGaN/GaN Gated-Edge Termination Schottky Barrier Diodes Under Continuous Switching Operation 连续开关操作下AlGaN/GaN栅极端端肖特基势垒二极管阱诱导的动态退化分析

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-08-06 DOI: 10.1109/TED.2026.3714751

Zhen-Hong Huang;Benoit Bakeroot;Olga Syshchyk;Ching-Chia Lee;Yu-Teng Tso;Pei-Jung Wang;Dirk Wellekens;Niels Posthuma;Sheng-Shiuan Yeh;Stefaan Decoutere;Tian-Li Wu

{"title":"Analysis of Trap-Induced Dynamic Degradation in AlGaN/GaN Gated-Edge Termination Schottky Barrier Diodes Under Continuous Switching Operation","authors":"Zhen-Hong Huang;Benoit Bakeroot;Olga Syshchyk;Ching-Chia Lee;Yu-Teng Tso;Pei-Jung Wang;Dirk Wellekens;Niels Posthuma;Sheng-Shiuan Yeh;Stefaan Decoutere;Tian-Li Wu","doi":"10.1109/TED.2026.3714751","DOIUrl":"https://doi.org/10.1109/TED.2026.3714751","url":null,"abstract":"This work investigates the dynamic switching characteristics of gated-edge termination (GET) Schottky barrier diodes (SBDs) fabricated on a 200-V GaN-on-SOI platform, with an emphasis on performance under continuous switching conditions. A wafer-level continuous-switching methodology is employed to characterize the dynamic <sc>on</small>-resistance and forward voltage under varying switching frequencies (100–300 kHz), duty cycles (30%–70%), <sc>off</small>-state switching voltages (up to 200 V), and temperatures (<inline-formula> <tex-math>$25~^{circ }$ </tex-math></inline-formula>C–<inline-formula> <tex-math>$125~^{circ }$ </tex-math></inline-formula>C). A capture-emission trapping model is used to extract time constants and explain the observed duty cycle- and temperature-dependent degradation behaviors. Through a systematic comparison of three field-plate configurations, the study reveals that an additional metal field plate effectively mitigates electric field crowding and trap occupation, which suppresses dynamic switching degradation. This work provides critical insights into the physical mechanisms governing degradation in AlGaN/GaN-based power SBDs, aiming to improve their dynamic switching stability.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5452-5459"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148902869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Strategy for Lift-Off Monitoring and Temperature Decoupling of IGBT Bond Wires Based on Crosstalk Gate Voltage 基于串扰栅极电压的IGBT键合线升空监测与温度解耦策略

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-23 DOI: 10.1109/TED.2026.3712722

Mingxing Du;Zhihao Zhang;Gengji Wang

{"title":"A Strategy for Lift-Off Monitoring and Temperature Decoupling of IGBT Bond Wires Based on Crosstalk Gate Voltage","authors":"Mingxing Du;Zhihao Zhang;Gengji Wang","doi":"10.1109/TED.2026.3712722","DOIUrl":"https://doi.org/10.1109/TED.2026.3712722","url":null,"abstract":"Bond wires lift-off is one of the primary aging modes in insulated gate bipolar transistor (IGBT) modules, which is prone to thermal runaway and system failures. This article focuses on the crosstalk effect in half-bridge IGBT modules, conducting an in-depth analysis of the undershoot phenomenon of crosstalk gate voltage and aiming to establish a bond wires health monitoring method based on the undershoot peak of crosstalk gate voltage, independent of junction temperature. Through theoretical modeling and equivalent circuit analysis, the dynamic changes of the crosstalk gate voltage were systematically derived, revealing the lift-off induced mechanism affecting crosstalk voltage while achieving temperature decoupling. The influence of critical factors—temperature, the load current, and the bus voltage—is discussed and quantified. The experimental results indicate that the node voltage under the crosstalk gate voltage can serve as a temperature sensitive electrical parameter (TESP) unaffected by bond wires aging, with a junction temperature sensitivity of 0.008 V/°C. Furthermore, the undershoot peak voltage decreases progressively with increasing aging degree of bond wires, with an average reduction of approximately 0.28 V per lift-off bond wire. This article achieves effective monitoring of IGBT module bond wires lift-off and junction temperature using a single parameter, providing a theoretical foundation and experimental evidence for real-time, nondestructive reliability condition monitoring.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5437-5444"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Degradation Mechanisms in p-Type Nanosheet FETs: Role of Source/Drain Doping, Stress, and Inner Spacer Interface Traps p型纳米片场效应管的性能退化机制：源/漏掺杂、应力和内部间隔层界面陷阱的作用

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-21 DOI: 10.1109/TED.2026.3711954

Lee-Chi Hung;Krishna K. Bhuwalka;Zlatan Stanojević;Franz Schanovsky;Hans Kosina;Markus Karner

{"title":"Performance Degradation Mechanisms in p-Type Nanosheet FETs: Role of Source/Drain Doping, Stress, and Inner Spacer Interface Traps","authors":"Lee-Chi Hung;Krishna K. Bhuwalka;Zlatan Stanojević;Franz Schanovsky;Hans Kosina;Markus Karner","doi":"10.1109/TED.2026.3711954","DOIUrl":"https://doi.org/10.1109/TED.2026.3711954","url":null,"abstract":"The performance of p-type nanosheet FETs (NSFETs) with embedded SiGe (eSiGe) source/drain (S/D) is investigated by solving the subband Boltzmann transport equation (SBTE), highlighting three detrimental effects of aggressive scaling: 1) insufficient extension doping; 2) stress relaxation during the merging of epitaxial growth fronts; and 3) interface trap density (Dit) at the Si/SiN interfaces. An optimal doping window of the first epitaxial layer (L1) between 5 × 1019 and 2 × 1020 cm−3 is identified to maintain gate-controlled operation. Below this range, the device enters the injection-limited transport regime, where stress relaxation and Dit-induced injection barriers are significantly amplified, leading to pronounced performance degradation. These results highlight the critical role of L1 doping optimization for effective stress engineering and Dit mitigation, and underscore the necessity of non-equilibrium transport modeling for highly-scaled NSFETs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5381-5386"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11615072","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Combined Interfacial Engineering With Pentafluorobenzoic Acid for High-Performance CsPbI3 Photodetectors 五氟苯甲酸复合界面工程用于高性能CsPbI3光电探测器

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-21 DOI: 10.1109/TED.2026.3712679

Lei Chen;Jiamin Zhang;Jun Qi;Yanrong Deng;Tangyou Sun;Yan Tian;Peihua Wangyang

{"title":"Combined Interfacial Engineering With Pentafluorobenzoic Acid for High-Performance CsPbI3 Photodetectors","authors":"Lei Chen;Jiamin Zhang;Jun Qi;Yanrong Deng;Tangyou Sun;Yan Tian;Peihua Wangyang","doi":"10.1109/TED.2026.3712679","DOIUrl":"https://doi.org/10.1109/TED.2026.3712679","url":null,"abstract":"All-inorganic CsPbI3 perovskites are promising for photodetectors (PDs) owing to their superior optoelectronic properties, yet their device performance is severely restricted by interfacial defects and poor energy-level alignment at the perovskite/electron transport layer (ETL) interface. In this work, we propose a combined interfacial modification strategy by integrating pentafluorobenzoic acid (PFBA) into a 1,4-butanediamine (BDA) interlayer, achieving simultaneous defect passivation and interfacial energy-level optimization in CsPbI3 films. The resultant PFBA-modified CsPbI3 PDs realize superior self-powered performance at zero bias, including a maximum responsivity of 0.47 A<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>W<inline-formula> <tex-math>${}^{-text{1}}$ </tex-math></inline-formula>, a specific detectivity of <inline-formula> <tex-math>$text{7.88} times text{10}^{text{12}}$ </tex-math></inline-formula> Jones, a broad linear dynamic range (LDR) of 141 dB, and a fast response speed (rise/fall time = 1.2/<inline-formula> <tex-math>$text{1.2}~mu $ </tex-math></inline-formula>s). Meanwhile, the dark current density is reduced by one order of magnitude (from <inline-formula> <tex-math>$text{1.7} times text{10}^{-text{4}}$ </tex-math></inline-formula> to <inline-formula> <tex-math>$text{1.8} times text{10}^{-text{5}}$ </tex-math></inline-formula> mA<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>cm<inline-formula> <tex-math>${}^{-text{2}}$ </tex-math></inline-formula>) at zero bias, and the device maintains 99.6% of its initial photocurrent density after 35 days of storage in a nitrogen-filled glove box. This work offers a reliable and effective interfacial engineering route for constructing high-performance and stable all-inorganic self-powered perovskite PDs.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5604-5608"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fabrication and Experimental Test of Low-Loss Waveguide Mode Converters for 0.34-THz Vacuum Electron Devices 0.34 thz真空电子器件低损耗波导模式变换器的制作与实验测试

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-08-18 DOI: 10.1109/TED.2026.3717561

Guo Guo;Zeyuan Yang;Haofei Li;Fei Shen;Yanyu Wei

{"title":"Fabrication and Experimental Test of Low-Loss Waveguide Mode Converters for 0.34-THz Vacuum Electron Devices","authors":"Guo Guo;Zeyuan Yang;Haofei Li;Fei Shen;Yanyu Wei","doi":"10.1109/TED.2026.3717561","DOIUrl":"https://doi.org/10.1109/TED.2026.3717561","url":null,"abstract":"The design, fabrication, and test of 0.34-THz rectangular TE10 to circular TE01 mode converters for vacuum electron devices are introduced in this article. This work features high operation frequency and low loss, and provides compact structure dimensions (shorter than 26.6 mm) and high transmission efficiency (higher than 96.8%). The main competing modes and mode converter processes are analyzed theoretically and optimized by the full-wave simulations. Following micromachining processes, the 0.34-THz serpentine waveguide mode converter is successfully fabricated and assembled. The fabrication errors are within <inline-formula> <tex-math>$2~mu $ </tex-math></inline-formula>m, and the surface roughness of the high-frequency structure is effectively controlled within <inline-formula> <tex-math>$0.1~mu $ </tex-math></inline-formula>m, respectively. The S-parameters of the back-to-back joined mode converters are experimentally tested. The results verified that the S11 are below −13 dB and S21 are better than −0.6 dB within the operation bandwidth, which indicates that the insertion losses for one mode converter are as low as 0.3 dB. Compared with previously reported THz-range TE01 mode converters, the proposed converter achieves the lowest measured insertion losses while maintaining a compact overall length. The test results are consistent with the updated simulation results by considering the actual surface roughness and fabrication errors. The miniaturized mode converters and their micromanufacture technologies indicate significant potential for vacuum electron devices in the millimeter-wave and terahertz spectrum.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5777-5782"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3-D-Microfabrication Millimeter-Wave Bandstop Filter for SatCom Application 用于卫星通信的三维微加工毫米波带阻滤波器

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-23 DOI: 10.1109/TED.2026.3714375

Jia-Hao Su;Hui-Kun Yang;Jin Xu;Hong Yu;Yan-Sen Zhao;Xiao Li;Jia-Hao Zhao

{"title":"3-D-Microfabrication Millimeter-Wave Bandstop Filter for SatCom Application","authors":"Jia-Hao Su;Hui-Kun Yang;Jin Xu;Hong Yu;Yan-Sen Zhao;Xiao Li;Jia-Hao Zhao","doi":"10.1109/TED.2026.3714375","DOIUrl":"https://doi.org/10.1109/TED.2026.3714375","url":null,"abstract":"This article presents 3-D-microfabrication millimeter-wave (mmWave) rectangular microcoaxial line (R<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>CL) bandstop filters (BSFs) with an inversed Chebyshev response, fabricated using the microstructure electrochemical fabrication (MEFAB) process. To achieve an equiripple stopband of the BSF, a low-pass prototype circuit with nonresonating nodes (NRNs) is applied to syn-thesize the inversed Chebyshev response. By leveraging the 3-D microfabrication of the MEFAB process, this design integrates both broadside and narrowside coupling structures between the resonators and the main feed line. In particular, the broadside coupling structures can enhance coupling, while the narrowside coupling structures enable a reduced footprint, thereby achieving a wider stopband and compact size for the proposed BSFs. As examples, a four-order mmWave uniform impedance resonator (UIR) BSF with an equiripple stopband attenuation of 30 dB is designed, fabricated, and measured. To further reduce the size, a four-order stepped impedance resonator (SIR) BSF is also designed, fabricated, and measured. The fabricated UIR BSF exhibits a measured center frequency of 29.44 GHz, a 30-dB stopband fractional bandwidth (FBW) of 12.9%, a minimum passband insertion loss (IL) of 0.54 dB, and a circuit size of <inline-formula> <tex-math>$8.471times 2.376times 0.9$ </tex-math></inline-formula> mm3. In comparison, the SIR BSF features a more compact size of <inline-formula> <tex-math>$7.673times 1.935times$ </tex-math></inline-formula> <inline-formula> <tex-math>$ 0.9$ </tex-math></inline-formula> mm3. The proposed R<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>CL BSFs offer low loss in the passband, wide stopband with high rejection, quasi-planar structure, and compact size, providing a promising solution for mmWave SatCom applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5823-5829"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Annealing-Tuned Barrier Height in Quasi-Vertical GaN Schottky Diodes for Microwatt Microwave Rectification 用于微瓦微波整流的准垂直GaN肖特基二极管的退火调谐势垒高度

IF 3.6 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2026-09-01 Epub Date: 2026-07-21 DOI: 10.1109/TED.2026.3713113

Yang Li;Xu Zhang;Zheng-Ning Gu;Qiu-Xuan Li;Ren-Pin Huang;Tao Liu;Zi-Hao Zhou;Die Xiao;Zhi-Wei Chen;Zhang-Cheng Liu;Feng-Qiu Jiang;Xiao Wang;Jin-Ping Ao

{"title":"Annealing-Tuned Barrier Height in Quasi-Vertical GaN Schottky Diodes for Microwatt Microwave Rectification","authors":"Yang Li;Xu Zhang;Zheng-Ning Gu;Qiu-Xuan Li;Ren-Pin Huang;Tao Liu;Zi-Hao Zhou;Die Xiao;Zhi-Wei Chen;Zhang-Cheng Liu;Feng-Qiu Jiang;Xiao Wang;Jin-Ping Ao","doi":"10.1109/TED.2026.3713113","DOIUrl":"https://doi.org/10.1109/TED.2026.3713113","url":null,"abstract":"This article proposes a thermal annealing strategy for Schottky barrier height (SBH) tuning in TiN-anode quasi-vertical gallium nitride (GaN) Schottky barrier diodes (SBDs) for microwatt microwave rectification. By annealing at <inline-formula> <tex-math>$200~^{circ } $ </tex-math></inline-formula>C, <inline-formula> <tex-math>$300~^{circ } $ </tex-math></inline-formula>C, and <inline-formula> <tex-math>$400~^{circ } $ </tex-math></inline-formula>C, the SBH is tuned from 0.332 to 0.392 eV in increments of approximately 0.02 eV. Based on theoretical analysis and experimental characterization, the barrier enhancement is found to be mainly associated with the reduction in interface-state density and the reconstruction of the TiN/GaN near-interface region during annealing. A 2.45-GHz microwave rectifier based on the barrier-optimized GaN SBD achieves a power conversion efficiency (PCE) of 52.5% at an input power of −11 dBm and retains 30% even at −20 dBm, showing significant improvement compared with the state of the art. These results demonstrate the effectiveness of thermal-annealing-enabled barrier tuning for microwatt microwave rectification and further confirm the potential of GaN SBDs for low-power microwave rectifier applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"73 9","pages":"5347-5353"},"PeriodicalIF":3.6,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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