IEEE Transactions on Electron Devices最新文献

{"title":"Current Collapse in Buffer-Free GaN-on-SiC Power Transistors: Maxwell-Wagner Effect and Related Model","authors":"Alberto Cavaliere;Nicola Modolo;Carlo De Santi;Christian Koller;Clemens Ostermaier;Gaudenzio Meneghesso;Enrico Zanoni;Olof Öberg;Qin Wang;Ding Yuan Chen;Anders Lundskog;Jr-Tai Chen;Matteo Meneghini","doi":"10.1109/TED.2025.3556052","DOIUrl":"https://doi.org/10.1109/TED.2025.3556052","url":null,"abstract":"Recently, the use of insulating substrates has emerged as a viable option for the fabrication of GaN power transistors exceeding 1 kV. Such structures are of interest because no doped buffer is used, so--ideally—a low dynamic <inline-formula> <tex-math>${R}_{text {DSON}}$ </tex-math></inline-formula> is expected. This article investigates the recoverable (and temperature dependent) current lowering induced by negative backgating in buffer-free GaN-on-SiC devices. Remarkably, we demonstrate that such an effect is not directly related to charge trapping, but to the Maxwell-Wagner effect, i.e., the charge migration at the interface between the insulating SiC substrate and the semi-insulating GaN layer. Accordingly, a model is defined and validated to simulate with great accuracy, the current decreases (and related kinetics) as a function of temperature, voltage, and time.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2252-2258"},"PeriodicalIF":2.9,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The γ-Ray TID Effect and Irradiation Damage Recovery on β-Ga₂O₃/Al₂O₃ MOSCAPs","authors":"Song Li;Mingchao Yang;Leidang Zhou;Liang Chen;Silong Zhang;Fangbao Wang;Zhang Wen;Songquan Yang;Ming Li;Weihao Liu;Li Geng;Yue Hao;Xiaoping Ouyang","doi":"10.1109/TED.2025.3552361","DOIUrl":"https://doi.org/10.1109/TED.2025.3552361","url":null,"abstract":"In this study, the impact of &lt;inline-formula&gt; &lt;tex-math&gt;$gamma $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-ray total ionizing dose (TID) irradiation on the electrical performance of beta-gallium oxide (&lt;inline-formula&gt; &lt;tex-math&gt;$beta $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-Ga2O3)/Al2O3 MOSCAPs was investigated, and a new irradiation damage recovery method was also proposed using the supercritical N2O (SCN2O) fluid postoxidation annealing (POA) process. After a cumulative &lt;inline-formula&gt; &lt;tex-math&gt;$gamma $ &lt;/tex-math&gt;&lt;/inline-formula&gt;-ray dose of 1.108 Mrad (SiO2), the net carrier concentration (&lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {d}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) decreased by 28.7%, and the interface state density (&lt;inline-formula&gt; &lt;tex-math&gt;${D} _{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) increased from &lt;inline-formula&gt; &lt;tex-math&gt;$4.41times 10^{{11}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; to &lt;inline-formula&gt; &lt;tex-math&gt;$5.12times 10^{{11}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; &lt;inline-formula&gt; &lt;tex-math&gt;${mathrm {eV}}^{-{1}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;&lt;inline-formula&gt; &lt;tex-math&gt;${mathrm {cm}}^{-{2}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, according to the frequency-dependent capacitance-voltage (C–V) measurements. Meanwhile, the effective trapped charge density (&lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {eff}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) was reduced from &lt;inline-formula&gt; &lt;tex-math&gt;$- 1.82times 10^{{12}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; to &lt;inline-formula&gt; &lt;tex-math&gt;$- 1.37times 10^{12}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; &lt;inline-formula&gt; &lt;tex-math&gt;${mathrm {eV}}^{-{1}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;&lt;inline-formula&gt; &lt;tex-math&gt;${mathrm {cm}}^{-{2}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, leading to a decreased flat-band voltage (&lt;inline-formula&gt; &lt;tex-math&gt;${V} _{text {fb}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;), which was attributed to the formation of positively charged oxide trapped charge (&lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {ot}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;). What is more, the forward leakage current density increased by ten times, and a 9.5% decrease in the breakdown voltage (&lt;inline-formula&gt; &lt;tex-math&gt;${V} _{text {br}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) was observed according to the current-voltage (I–V) measurements. Moreover, the leakage current analysis indicated that the changes in the I–V characteristics were primarily caused by variations in &lt;inline-formula&gt; &lt;tex-math&gt;${D} _{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; and &lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {ot}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;. In addition, after the SCN2O POA process at &lt;inline-formula&gt; &lt;tex-math&gt;$120~^{circ }$ &lt;/tex-math&gt;&lt;/inline-formula&gt;C, the damages of the irradiated device can be repaired. Specifically, the material properties, such as &lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {d}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, &lt;inline-formula&gt; &lt;tex-math&gt;${D} _{text {it}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, and &lt;inline-formula&gt; &lt;tex-math&gt;${N} _{text {eff}}$ &lt;/tex-math&gt;&lt;/inline-formula&gt;, and the electrical properties of &lt;inline-formula&gt; &lt;tex-math&gt;${V} _","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2220-2225"},"PeriodicalIF":2.9,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3-D On-Chip Integration of GaN Power Devices on Power Delivery Network (PDN) With Direct Heat Spreading Layer Bonding for Heterogeneous 3-D (H3D) Stacked Systems","authors":"Jaeyong Jeong;Chan Jik Lee;Sung Joon Choi;Nahyun Rheem;Minseo Song;Yoon-Je Suh;Bong Ho Kim;Joon Pyo Kim;Joonsup Shim;Jiseon Lee;Myungsoo Park;Yumin Koh;Donghyun Kim;Sanghyeon Kim","doi":"10.1109/TED.2025.3556044","DOIUrl":"https://doi.org/10.1109/TED.2025.3556044","url":null,"abstract":"Heterogeneous 3-D (H3D) stacked systems offer numerous advantages for high-performance computing (HPC) and artificial intelligence/machine learning (AI/ML) applications. However, implementing H3D systems requires a re-designed power delivery network (PDN) for efficient power delivery in 3-D stacked systems and thermal management solutions. To develop an efficient PDN for the H3D system, a 3-D integrated on-chip power device is recommended. In this work, we demonstrate an H3D-integrated GaN power device on the PDN of a CMOS chip with direct heat-spreading layer bonding. The GaN power devices were designed to integrate both E-mode and D-mode with <inline-formula> <tex-math>${L}_{text {G}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$1.5~mu $ </tex-math></inline-formula> m and <inline-formula> <tex-math>${L}_{text {GD}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$15~mu $ </tex-math></inline-formula> m, and achieve a <inline-formula> <tex-math>${R}_{scriptscriptstyle{mathrm {on}}}$ </tex-math></inline-formula> of <inline-formula> <tex-math>$22.3~Omega $ </tex-math></inline-formula> mm and <inline-formula> <tex-math>${V}_{text {BD}}$ </tex-math></inline-formula> of 137 V. These results surpass the limitation of silicon-based power devices. In addition, we experimentally demonstrated that direct heat spreading layer bonding effectively relaxed the thermal effect of H3D-integrated GaN power devices using a thermoreflectance microscopy (TRM) system for the first time. By introducing a heat spreading layer, the thermal resistance (<inline-formula> <tex-math>${R}_{text {TH}}$ </tex-math></inline-formula>) of the GaN power device was reduced by 48.8% compared to GaN power devices without a heat spreading layer. These findings mark a substantial advancement in PDN technology, setting the stage for vertically integrated active PDNs that support efficient power delivery and effective thermal management in H3D stacked systems.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2654-2661"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Graph Representation Framework for Accelerating Atomic-Level Semiconductor Device Simulation","authors":"Tengfei Wang;Zifeng Wang;Jin He;Hao Wang;Sheng Chang","doi":"10.1109/TED.2025.3556051","DOIUrl":"https://doi.org/10.1109/TED.2025.3556051","url":null,"abstract":"This article proposes a machine-learning (ML) method to accelerate atomic-level device simulation. The main idea is to utilize graph convolutional network (GCN) to predict the potential distribution of the device, aiming to expedite the time-consuming self-consistent calculation process of the transport-Poisson equation within the nonequilibrium Green’s function (NEGF) method. Using the network-predicted electrostatic potential distribution as the initial solution can accelerate the convergence speed of the above process without compromising the accuracy of NEGF calculations. Most importantly, this network introduces a new method for device representation using graphs. It explicitly encodes the coupling effect between the device’s scattering region (SR) and electrodes while effectively capturing quantum mechanical effects at the atomic level. This method offers a more reliable and physically significant approach to device encoding, providing fresh insights on merging ML with atomic-level device simulations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2625-2632"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Si–Ge Axial Heterojunction RFET With Enhanced On-State Current and Low Subthreshold Swing","authors":"Pengjun Wan;Bo Zhang;Yuxin Ran;Siying Zheng;Yi Li;Jiuren Zhou;Jie Liang","doi":"10.1109/TED.2025.3556111","DOIUrl":"https://doi.org/10.1109/TED.2025.3556111","url":null,"abstract":"This article investigates Si and Ge dual-gate reconfigurable field-effect transistors (DG-RFETs) at the nanoscale. It is found that while the Ge DG-RFET improves the <sc>on</small>-state saturated current (<inline-formula> <tex-math>${I}_{text {ON} }$ </tex-math></inline-formula>) of the Si DG-RFET, it also generates bipolar currents at low voltages, which increase as the device size decreases. By analyzing the conduction mechanism of the DG-RFET and examining the source of the bipolar currents in Ge DG-RFETs, we propose a silicon-germanium axial heterojunction RFET (Si-Ge AH-RFET). The conduction mechanism was investigated in detail by Sentaurus TCAD, which revealed a unique double-tunneling mechanism in the P-program. Simulation results show that compared with Si DG-RFETs, <inline-formula> <tex-math>${I}_{text {ON} }$ </tex-math></inline-formula> of the proposed Si-Ge AH-RFET is improved by approximately eight times in the N-program and about 11 times in the P-program and the subthreshold swing (SS) is significantly reduced. Meanwhile, it does not exhibit the same bipolar currents at low voltages as the Ge DG-RFET and maintains the low leakage current (<inline-formula> <tex-math>${I}_{text {OFF} }$ </tex-math></inline-formula>) as the Si DG-RFET. Furthermore, compared with the Si DG-RFET, the transmission delay of the Si-Ge AH-RFET-based inverter is reduced by approximately 75%.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2640-2646"},"PeriodicalIF":2.9,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Frequency Noise Investigation of Organic Field-Effect Transistors Based on N-Type Donor-Acceptor Conjugated Copolymer","authors":"Lijian Chen;Quanhua Chen;Hong Zhu;Walid Boukhili;Binhong Li;Xing Zhao;Chee Leong Tan;Huabin Sun;Stefan Mannsfeld;Yong Xu;Dongyoon Khim","doi":"10.1109/TED.2025.3555262","DOIUrl":"https://doi.org/10.1109/TED.2025.3555262","url":null,"abstract":"Organic field-effect transistors (OFETs) based on n-type donor-acceptor (D-A) conjugated copolymer are at the forefront of research in organic electronics. Yet, an understanding of the fundamental aspects of their charge transport, in particular the relevant traps, remains limited. In this study, we show that the low-frequency noise (LFN) of n-type OFETs based on N2200 exhibits 1/f behavior. The normalized power spectrum density of the drain current (<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>), namely (<inline-formula> <tex-math>${S} _{text {Id}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}^{{2}}$ </tex-math></inline-formula>), varies similarly as (<inline-formula> <tex-math>${g} _{text {m}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I} _{text {D}}$ </tex-math></inline-formula>)2 with gm being the transconductance, indicating the carrier number fluctuations. Examination on the annealing temperature and air stability of the devices with different contacts using LFN reveal sizably varied trap density, conforming the correlation between performance degradation and defect states. Thus, LFN provides quantitative insight into the charge transport behind.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2747-2750"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monolithic 3-D Integration of Diverse Memories: Resistive Switching (RRAM) and Gain Cell (GC) Memory Integrated on Si CMOS","authors":"Shuhan Liu;Robert M. Radway;Xinxin Wang;Filippo Moro;Jean-Francois Nodin;Koustav Jana;Lixian Yan;Shuting Du;Luke R. Upton;Wei-Chen Chen;Jimin Kang;Jian Chen;Haitong Li;Francois Andrieu;Elisa Vianello;Priyanka Raina;Subhasish Mitra;H.-S. Philip Wong","doi":"10.1109/TED.2025.3556113","DOIUrl":"https://doi.org/10.1109/TED.2025.3556113","url":null,"abstract":"The future memory is massive, diverse, and tightly integrated with computing. This research presents tight integration, both physically and architecturally, of two on-chip memory technologies, resistive switching random access memory (RRAM) and gain cell (GC) memory. HfO2 RRAM and indium tin oxide (ITO) GC memory are monolithically integrated on 130-nm Si CMOS technology to form a joint memory that enables low-energy training and low-standby-power inference for edge devices. High-bandwidth on-chip data transfer can have a bandwidth that is <inline-formula> <tex-math>$90times $ </tex-math></inline-formula> state-of-the-art (SoTA) HBM3E and <inline-formula> <tex-math>$211times $ </tex-math></inline-formula> PCIe 7.0, enabled by high-density monolithic 3-D interconnections between memory arrays and high-speed transfer circuit within the integrated joint memory macro. Fabricated atomic layer deposition (ALD) ITO FET exhibits positive <inline-formula> <tex-math>${V}_{text {TH}}$ </tex-math></inline-formula> of 0.67 V, excellent subthreshold slope (SS) of 65 mV/dec, high <sc>on</small>-current of <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, and low <sc>off</small>-current of <inline-formula> <tex-math>$5times 10^{-{18}}$ </tex-math></inline-formula> A/<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m, as extracted from >5000 s retention. The joint memory macro consumes 78% less standby power and 95% less training energy for MobileBERT compared to SRAM with iso-capacity. This RRAM-GC joint memory facilitates efficient continual learning in edge devices, addressing the challenges of a resource-constrained environment while supporting adaptive artificial intelligence (AI) model updates.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2685-2690"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Back-Gate Bias on the Total Ionizing Dose and Hot Carrier Injection Effects in Double SOI nMOSFETs","authors":"Yuan Gao;Zihan Wang;Yongwei Chang;Zhongying Xue;Xing Wei","doi":"10.1109/TED.2025.3552744","DOIUrl":"https://doi.org/10.1109/TED.2025.3552744","url":null,"abstract":"Double silicon-on-insulator (DSOI) device exhibits high tolerance to total ionizing dose (TID) effect due to back gate bias (<inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>) modulation. Negative <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the performance degradation caused by the TID effect, while positive <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula> is required to compensate for the degradation caused by hot carrier injection (HCI) effect. This article focuses on the synergistic effect between TID and HCI under different back-gate voltage and modulation effect of <inline-formula> <tex-math>${V}_{text {bg}}$ </tex-math></inline-formula>. The HCI effect is exacerbated by TID effect owing to the trapped charges in the oxide, which enhance the impact of ionizing in channel region. <inline-formula> <tex-math>${Delta } {V}_{text {th}}$ </tex-math></inline-formula> [<inline-formula> <tex-math>${V}_{text {th}}$ </tex-math></inline-formula> at 3 Mrad(Si) <inline-formula> <tex-math>$- {V}_{text {th}}$ </tex-math></inline-formula> at 0 Mrad(Si)] of DSOI MOSFET without stress is approximately −0.215 V, larger than that of stressed device. Additionally, applying a back-gate bias to mid-Si is an effective method to suppress the degradation in synergistic experiments.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2159-2164"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tailoring Ferroelectric Performance and Domain Structure Ordering in HZO Capacitors via 2D-WS2 Multifunctional Layer","authors":"Seungkwon Hwang;Hojung Jang;Kyumin Lee;Laeyong Jung;Jongwon Yoon;Jung-Dae Kwon;Kyung Song;Yonghun Kim;Hyunsang Hwang","doi":"10.1109/TED.2025.3553822","DOIUrl":"https://doi.org/10.1109/TED.2025.3553822","url":null,"abstract":"In this study, we propose a high-performance and reliable ferroelectric capacitor based on Hfx <inline-formula> <tex-math>$Zr_{{1}-{x}}$ </tex-math></inline-formula>O2 (HZO) integrated with an ultrathin multifunctional 2D-WS2 layer. The WS2 layer, positioned at the interface between the bottom electrode and HZO, serves a multiple function. First, the WS2 acts as a protective layer, effectively suppressing the formation of interfacial defects, such as oxygen vacancies and dead layers during the device fabrication process. Second, this layer functions as a seed layer, promoting the growth of vertically aligned HZO domain structures and enhancing the ferroelectric crystallinity of HZO. This approach addresses key limitations in conventional HZO, including interfacial instability, random domain distribution, and inconsistent switching behavior. Our experimental results reveal significant improvements in ferroelectric performance, achieving stable endurance exceeding <inline-formula> <tex-math>$10^{{12}}$ </tex-math></inline-formula> cycles while maintaining a high remanent polarization (<inline-formula> <tex-math>$2P_{text {r}} gt 50~mu $ </tex-math></inline-formula> <inline-formula> <tex-math>$C/cm^{{2}}$ </tex-math></inline-formula>). Additionally, long-term retention performance is expected to exceed ten years at <inline-formula> <tex-math>$85~^{circ }$ </tex-math></inline-formula>C. Furthermore, the integration of a WS2 interface layer demonstrates excellent device-to-device uniformity and consistency, even in nanoscale HZO device structures. This work provides new insights into the development of high-performance ferroelectric nonvolatile memory technology by highlighting the multiple advantages of the WS2 layer, which enhances interface stability and facilitates vertical domain alignment.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2700-2707"},"PeriodicalIF":2.9,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Elucidating the Role of Ferroelectric in Memory Window Expansion of Ferroelectric FETs With Gate-Side Injection","authors":"Yixin Qin;Saikat Chakraborty;Zijian Zhao;Sizhe Ma;Moonyoung Jung;Kijoon Kim;Suhwan Lim;Kwangyou Seo;Kwangsoo Kim;Wanki Kim;Daewon Ha;Xiao Gong;Vijaykrishnan Narayanan;Jaydeep P. Kulkarni;Kai Ni","doi":"10.1109/TED.2025.3552013","DOIUrl":"https://doi.org/10.1109/TED.2025.3552013","url":null,"abstract":"In this work, we present a comprehensive experimental and modeling study to clarify the role of the ferroelectric (FE) layer in enhancing the memory window (MW) of FeFETs with gate-side charge injection. We separated the FE contributions to the MW into remnant polarization and top charge trap layer (CTL) trapping. Our findings demonstrate that: 1) FE layer expands the MW in two ways: by enhanced FE polarization induced by gate-side charge trapping into the CTL and through their superlinear <inline-formula> <tex-math>${Q} {_{text {FE}}}$ </tex-math></inline-formula>–<inline-formula> <tex-math>${V} {_{text {FE}}}$ </tex-math></inline-formula> relationship that boosts the CTL electric field and enhances charge trapping; 2) the contributions from polarization and CTL trapping mutually reinforce each other, resulting in a larger MW compared to a FE + dielectric stack or a high-<inline-formula> <tex-math>${k} +$ </tex-math></inline-formula> CTL stack, where, in both stacks, only one factor is active; 3) enhanced polarization strengthens the channel interfacial layer electric field, suppressing electron detrapping from the channel and, thus, enabling immediate read-after–write, thereby improving FeFET read throughput; and 4) the MW can be further increased incorporating a blocking oxide layer above the CTL, achieving a 12-V window with a 2-nm-thick Al2O3 layer.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2708-2715"},"PeriodicalIF":2.9,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143949303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}