IEEE Transactions on Electron Devices最新文献

Ultrawide Band Gap Semiconductor Devices for RF, Power and Optoelectronic Applications 用于射频、功率和光电子应用的超宽带隙半导体器件

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-25 DOI: 10.1109/TED.2025.3585331

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Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on Wide Band Gap Semiconductors for Automotive Applications 《汽车用宽带隙半导体电子器件》特刊征文

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-25 DOI: 10.1109/TED.2025.3585327

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IEEE Transactions on Electron Devices Information for Authors IEEE电子器件信息汇刊

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-25 DOI: 10.1109/TED.2025.3585333

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IEEE Transactions on Electron Devices Publication Information IEEE电子设备出版信息汇刊

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-25 DOI: 10.1109/TED.2025.3585325

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Reliability of Advanced Nodes 高级节点可靠性

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-25 DOI: 10.1109/TED.2025.3585329

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Toward Generation of Megawatt Subnanosecond Microwave Pulses With High Repetition Rate 高重复频率的兆瓦亚纳秒微波脉冲的产生

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-22 DOI: 10.1109/TED.2025.3579437

Zhiyuan Zhang;Weijie Wang;Ruoyang Pan;Yelei Yao;Wei Jiang;Zewei Wu;Youlei Pu;Jianxun Wang;Yong Luo;Guo Liu

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Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling 面向1nm EOT的二维CMOS标化TMD晶体管栅极介质的表征方法

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-15 DOI: 10.1109/TED.2025.3586220

Chelsey Dorow;Aniruddha Konar;Ande Kitamura;Ashish Penumatcha;Sudarat Lee;Adedapo Oni;Chi-Yin Cheng;Nazmul Arefin;Kevin O'Brien;Scott B. Clendenning;David Kencke;Uygar Avci

{"title":"Characterization Methods of TMD Transistor Gate Dielectrics Targeting 1 nm EOT for 2-D CMOS Scaling","authors":"Chelsey Dorow;Aniruddha Konar;Ande Kitamura;Ashish Penumatcha;Sudarat Lee;Adedapo Oni;Chi-Yin Cheng;Nazmul Arefin;Kevin O'Brien;Scott B. Clendenning;David Kencke;Uygar Avci","doi":"10.1109/TED.2025.3586220","DOIUrl":"https://doi.org/10.1109/TED.2025.3586220","url":null,"abstract":"2-D materials show promise to possibly replace Si channel material to continue Moore’s Law scaling of transistors down to 5 nm gate lengths. The scaling opportunities of 2-D materials arise due to their ultra-thin monolayer thickness of sub-1 nm, which allows for strong electrostatic gate control while maintaining high mobility with virtually no surface roughness scattering from the intrinsically passivated van der Waals (vdW) surfaces. The scaling benefits of 2-D materials, however, can only be realized with the development of a highly scaled, low-defect gate oxide growth method compatible with vdW surfaces. This has thus far proven to be challenging as the vdW surfaces lack the dangling bonds required for standard ALD oxide growth nucleation. Furthermore, gate oxide films grown on vdW surfaces are rarely characterized following industry standard capacitance–voltage (CV) methods, primarily due to high leakage or resistance often present in today’s 2-D transistors, rendering CV measurements very difficult. While 2-D MOSFET gate leakage and contact resistances are improving rapidly, researchers still resort to inferring equivalent oxide thickness (EOT) from I–V characterization rather than standard CV. In this work, we show through both technology computer aided design (TCAD) simulations and experiments that I–V based methods of 2-D MOSFET EOT measurements have several pitfalls which may lead to inaccurate conclusions. We provide techniques to improve accuracy for both I–V and CV-based gate oxide characterization, which will help accelerate the field of 2-D transistor development closer toward a feasible CMOS technology.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"3974-3980"},"PeriodicalIF":2.9,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K SiC衬底上具有钨栅极和高离子/ IOFF比的性能增强p沟道GaN MESFET工作在525 K

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3584327

Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang

{"title":"A Performance-Enhanced p-Channel GaN MESFET With Tungsten Gate and High ION/ IOFF Ratio on SiC Substrate Operational at 525 K","authors":"Huake Su;Tao Zhang;Shengrui Xu;Yachao Zhang;Hongchang Tao;He Yang;Jingyu Jia;Yue Hao;Jincheng Zhang","doi":"10.1109/TED.2025.3584327","DOIUrl":"https://doi.org/10.1109/TED.2025.3584327","url":null,"abstract":"In this letter, a normally-off p-channel GaN metal–semiconductor field-effect transistor (MESFET) on SiC substrate with high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio and barrier-freed ohmic contact was first demonstrated. Compared to the polarization-enhanced p-GaN/AlN/AlGaN on Si substrate, the same designed epitaxial wafer on SiC substrate showed a decreased surface potential from 11 to −368 mV as well as 1.9 times lower contact resistance (<inline-formula> <tex-math>${R}_{C}text {)}$ </tex-math></inline-formula>, modulated by dislocation-related potential. Meanwhile, high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$3.3times 10^{{7}}$ </tex-math></inline-formula>, ultralow hysteresis voltage of 0.05 V, and subthreshold swing (SS) of 83 mV/dec were obtained. The well-behaved characteristics of p-channel GaN MESFET on SiC substrate with negligible turn-on voltage and high <inline-formula> <tex-math>${I}_{text {ON}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>${I}_{text {OFF}}$ </tex-math></inline-formula> ratio show great potential for low-voltage complementary metal–oxide–semiconductor (CMOS) applications.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 8","pages":"4558-4562"},"PeriodicalIF":2.9,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144705036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Full-Bridge Vortex-Type Tunneling Magnetoresistive Sensor on a Single Die 单模全桥涡隧道磁阻传感器

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3579462

Wei Su;Jiaming Liu;Xianfeng Liang;Mengmeng Guan;Jieqiang Gao;Haifeng Gao;Zhiguang Wang;Jinghong Guo;Zhongqiang Hu;Ming Liu

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Effects of Passivation Layers on the Characteristics and Stability of Indium–Gallium–Zinc Oxide Thin-Film Transistors 钝化层对铟镓锌氧化物薄膜晶体管特性和稳定性的影响

IF 2.9 2区工程技术

IEEE Transactions on Electron Devices Pub Date : 2025-07-11 DOI: 10.1109/TED.2025.3582235

Yuzhen Zhang;Qiuxiao Feng;Wangran Wu;Runxiao Shi;Weifeng Sun;Man Wong

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